Successive-approximation ADC

From testwiki
Jump to navigation Jump to search

Template:Short description

1978 integrated circuit containing an 8-bit successive-approximation analog-to-digital converter (Analog Devices AD570)

A successive-approximation ADC (or SAR ADC) is a type of analog-to-digital converter (ADC) that digitizes each sample from a continuous analog waveform using a binary search through all possible quantization levels.

Structure

Successive-approximation ADC block diagram showing digital-to-analog converter (DAC), end of conversion indicator (EOC), successive-approximation register (SAR), sample and hold circuit (S/H), input voltage (Template:Math) and reference voltage (Template:Math)

A successive-approximation analog-to-digital converter contains several component subcircuits:

  1. An analog voltage comparator that compares Template:Math to the output of a digital-to-analog converter (DAC).
  2. A successive-approximation register that is updated by the results of the comparator to provide the DAC with a digital code whose accuracy increases with each successive iteration.
  3. A DAC that supplies the comparator with an analog voltage relative to the reference voltage Template:Math (which corresponds to the full-scale range of the ADC) and proportional to the digital code of the SAR.

In many implementations, a sample-and-hold circuit is used to acquire the input voltage prior to starting a conversion. This holds the acquired voltage steady while a conversion is in progress. It is required if Template:Math can change rapidly enough to cause conversion errors, and is inherently an integral part of some types of ADCs (e.g., charge-redistribution ADC). Template:Clear

Algorithm

Drummer and Ray described the algorithm as applied to a digital voltmeter.[1] This paper predates ADC integrated circuits but describes the binary search decision-making.

The successive-approximation register is initialized with 1 in the most significant bit (MSB) and zeroes in the lower bits. The register's code is fed into the DAC, which provides an analog equivalent of its digital code (initially Template:Math) to the comparator for comparison with the sampled input voltage. If this analog voltage exceeds Template:Math, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1, and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximated output of the sampled input voltage.

  • Animation of a 4-bit successive-approximation ADC with Template:Math
    Animation of a 4-bit successive-approximation ADC with Template:Math
  • Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the x axis, starting with the initial state at notch 1. Voltages on the y axis.
    Operation of successive-approximation ADC as input voltage falls from 5 to 0 V. Iterations on the x axis, starting with the initial state at notch 1. Voltages on the y axis.

The algorithm's objective for the Template:Math iteration is to approximately digitize the input voltage to an accuracy of Template:Frac relative to the reference voltage. To show this mathematically, the normalized input voltage is represented as Template:Math in Template:Math by letting Template:Math. The algorithm starts with an initial approximation of Template:Math and during each iteration Template:Math produces the following approximation:

Template:Math approximation: Template:Math

where the binary signum function Template:Math mathematically represents the comparison of the previous iteration's approximation Template:Math with the normalized input voltage Template:Math:sgn(xi−1−x)={+1if xi−1≥x,−1if xi−1<x.It follows using mathematical induction that the approximation of the Template:Math iteration theoretically has a bounded accuracy of: Template:Math.

Examples

Example 9-bit ADC

The steps to converting an analog input to 9-bit digital, using successive-approximation, are shown here for all voltages from 5 V to 0 V in 0.1 V iterations. Since the reference voltage is 5 V, when the input voltage is also 5 V, all bits are set. As the voltage is decreased to 4.9 V, only some of the least significant bits are cleared. The MSB will remain set until the input is one half the reference voltage, 2.5 V.

The binary weights assigned to each bit, starting with the MSB, are 2.5, 1.25, 0.625, 0.3125, 0.15625, 0.078125, 0.0390625, 0.01953125, 0.009765625. All of these add up to 4.990234375, meaning binary 111111111, or one LSB less than 5.

When the analog input is being compared to the internal DAC output, it effectively is being compared to each of these binary weights, starting with the 2.5 V and either keeping it or clearing it as a result. Then by adding the next weight to the previous result, comparing again, and repeating until all the bits and their weights have been compared to the input, the result, a binary number representing the analog input, is found.

Example 4-bit ADC

The working of a 4-bit successive-approximation ADC is illustrated below. The MSB is initially set to 1, whereas the remaining digits are set to zero. If the input voltage is lower than the value stored in the register, on the next clock cycle, the register changes its value to that illustrated in the figure by following the green line. If the input voltage is higher, then on the next clock cycle, the register changes its value to that illustrated in the figure by following the red line. The simplified structure of this type of ADC that acts on Template:Math volts range can be expressed as an algorithm:

  1. Initialize register with MSB set to 1 and all other values set to zero.
  2. In the nTemplate:Sup clock cycle, if voltage is higher than digital equivalent voltage of the number in register, the (n+1)Template:Sup digit from the left is set to 1. If the voltage were lower than digital equivalent voltage, then nTemplate:Sup digit from left is set to zero and the next digit is set to 1. To perform a conversion, an N-bit ADC requires N such clock cycles, excluding the initial state.

Template:Multiple image

Conceptually, the successive-approximation algorithm initially assigns each digital output to a corresponding voltage range (see above). The algorithm effectively divides the range into two subranges and selects the subrange that the input voltage falls within, thus producing one bit of the result. This divide-and-select process is repeated for each previously selected subrange until all bits have been generated.

Inaccuracies in non-ideal analog circuits

DAC inaccuracy or electronic noise (or both) can cause the binary search algorithm to incorrectly set or clear a bit during a conversion, thus causing subsequently converted bits to also be incorrect and resulting in a binary output that differs significantly from the correct value. To avoid this, the DAC must generate an accurate output voltage for each of its Template:Math binary input values. Manufacturers may characterize the DAC accuracy in terms of effective number of bits (ENOB) rather than the actual number of output bits.

Template:As of, the component-matching limitations of the DAC generally limited the linearity to about 12 bits in practical designs and mandated some form of trimming or calibration to achieve the necessary linearity for more than 12 bits.[2] And since kT/C noise is inversely proportional to capacitance, low noise demands a large input capacitance (which costs chip area and requires a more powerful drive buffer), which has motivated proposals around noise cancellation.[3] For comparison, for a Template:Math of 5 V, the least significant bit of a 16-bit converter corresponds to 76 μV, which is around the 64 μVrms noise of a 1 pF (large for on-chip) capacitor at room temperature. Template:As of, SAR ADCs are limited to 18 bits, while delta-sigma ADCs (which can be 24 bits) are better suited if more than 16 bits are needed.[4] SAR ADCs are commonly found on microcontrollers because they are easy to integrate into a mixed-signal process, but suffer from inaccuracies from the internal reference voltage resistor ladder and clock and signal noise from the rest of the microcontroller, so external ADC chips may provide better accuracy.[5]

Calibration of the element weights allows for greater accuracy, but generally, some redundancy is then required.[6]

Charge-redistribution, successive-approximation ADC

Switched capacitor array acting as the DAC for an Template:Math-bit charge-redistribution SAR ADC, fed into a ground-referenced comparator.

A charge-redistribution, successive-approximation ADC employs a switched capacitor array to perform the functions of both sample-and-hold and DAC. It has a charge-scaling DAC consisting of an array of individually-switched capacitors, sized in powers of two, and an additional duplicate of the smallest capacitor, resulting in a total of Template:Math capacitors for Template:Math bits.[7] Thus if the largest capacitance is Template:Math, then the array's total capacitance is Template:Math.

Redistributing the capacitors' charge will adjust their net voltage, which is fed into the negative input of a comparator (whose positive input is always grounded) to perform the binary search using the following steps:[8][9]

3 bit capacitive ADC, using Template:Math. The bottom left transient simulation uses Template:Math or about Template:Math of Template:Math, resulting in an answer of Template:Math (101 in binary), representing Template:Math or Template:Math of Template:Math. "PESE" is the voltage on the array, and its remaining final voltage is the conversion's residual error.
  1. Discharge: The capacitors are discharged. Discharging to the comparator's offset voltage will automatically provide offset cancellation.
  2. Sampling: The capacitors are switched to the input signal Template:Math. After a brief sampling period, the capacitors will hold a charge equal to their respective capacitance times Template:Math (and minus the offset voltage upon each of them), so the array holds a total charge of Template:Math.
  3. Hold: The capacitors are switched to ground. This provides the comparator's negative input with a voltage of Template:Math.
  4. Conversion: the actual conversion process proceeds with the following steps in each iteration, starting with the largest capacitor as the test capacitor for the MSB, and then testing each next smaller capacitor in order for each bit of lower significance:
    1. Redistribution: The current test capacitor is switched to Template:Math. The test capacitor forms a charge divider with the remainder of the array, whose ratio depends on the capacitor's relative size. In the first iteration, the ratio is Template:Math, so the comparator's negative input becomes Template:Math. On the Template:Math iteration, the ratio will be Template:Math, so the Template:Math iteration of this redistribution step effectively adds Template:Math to the voltage.
    2. Comparison: The comparator's output determines the bit's value for to the current test capacitor. In the first iteration, if Template:Math is greater than Template:Frac, then the comparator will output a digital 1 and otherwise output a digital 0.
    3. Update Switch: A digital 1 result will leave the current test capacitor connected to Template:Math for subsequent iterations, while a digital 0 result will switch the capacitor back to ground. Thus, each Template:Math iteration may or may not add Template:Math to the comparator's negative input voltage. For instance, the voltage at the end of the first iteration will be Template:Math.
  5. End Of Conversion: After all capacitors are tested in the same manner, the comparator's negative input voltage will have converged as close as possible (given the resolution of the DAC) to the comparator's offset voltage.

Calibration

The capacitors must be calibrated for accuracy of 10 bits or more.Template:Cn A patent by assignee Cirrus Logic describes a method for calibrating such capacitors.[10]

History

The SAR ADC was first used for experimental pulse-code modulation (PCM) by Bell Labs in the 1940s. In 1954, Bernard Gordon introduced the first commercial vacuum tube SAR ADC, converting 50,000 11-bit samples per second.[11]

See also

References

Template:Reflist

Further reading

  • CMOS Circuit Design, Layout, and Simulation, 3rd Edition; R. J. Baker; Wiley-IEEE; 1208 pages; 2010; Template:ISBN
  • Data Conversion Handbook; Analog Devices; Newnes; 976 pages; 2004; Template:ISBN
  1. ↑ Template:Cite journal
  2. ↑ Template:Cite web
  3. ↑ Template:Cite journal
  4. ↑ Template:Cite web
  5. ↑ Template:Cite web
  6. ↑ Template:Cite patent
  7. ↑ Template:Cite book
  8. ↑ Template:Cite web
  9. ↑ Template:Cite web
  10. ↑ Template:Cite patent
  11. ↑ Template:Cite web
Retrieved from "https://en.wiki.beta.math.wmflabs.org/w/index.php?title=Successive-approximation_ADC&oldid=16992"