Short-channel effect

Template:Short description In electronics, short-channel effects occur in MOSFETs in which the channel length is comparable to the depletion layer widths of the source and drain junctions. These effects include, in particular, drain-induced barrier lowering, velocity saturation, quantum confinement and hot carrier degradation.

Electrostatic effects

Electrostatic short-channel effects arise in a planar NMOS when the electrical channel length ($L$) becomes short enough for the source and drain to exert significant electrostatic influence over the channel, reducing the gate’s relative control over the channel potential. Controlling the source–channel barrier in a planar long-channel NMOS is the gate-to-source voltage ($V_{GS}$). Under the simplified ideal long-channel conditions used here, the threshold voltage ($V_T$) is independent of the NMOS’s channel length and is represented as a function of the gate-oxide thickness ($x_{ox}$) and the acceptor doping concentration of its p-type body ($N_A$). The threshold-voltage dependence in a long-channel NMOS is thus represented by:

$V_T=f(x_{ox},N_A)$

Within a long-channel NMOS in the cutoff state—where $V_{GS}$ is below $V_T$—the source–channel barrier strongly suppresses the flow of electrons into the channel, albeit a smaller subthreshold current can still flow. When $V_{GS}$ is sufficiently high, the source–channel barrier is lowered, and the conduction-band edge ($E_C$; the energy landscape experienced by electrons) of the channel is thus closer to the $E_C$ of the source. When the channel’s $E_C$ is sufficiently low, the inversion electron concentration ($n_s$) reaches a sufficiently high level for the inversion threshold condition to be met, and the corresponding value of $V_{GS}$ is $V_T$.

However, in this simplified short-channel model, when $L$ becomes sufficiently small, the depletion regions of the source and drain begin overlapping underneath the channel. $V_T$ is now also dependent on the channel length and source/drain junction depth ($x_j$), where:

$V_T=f(x_{ox},N_A,L,x_j)$

Changes in $V_T$ ($\mathrm{\Delta }{V}_T$) depend on the relative strength of lateral electrostatics versus transverse electrostatics. The gate controls the channel from above through transverse electrostatics, while the source and drain influence the channel from its ends through lateral electrostatics. The electrostatic problem therefore becomes two-dimensional in a short-channel NMOS. The central channel is now no longer well isolated from source and drain influence; these influences extend into the middle and the gate cannot control the channel potential as independently or uniformly. This is described as “electrostatic integrity”, which is the extent to which the gate maintains effective control over the channel potential. A short-channel NMOS thus has reduced electrostatic integrity as lateral source and drain electrostatics become stronger relative to transverse gate control.

The division of electrostatic control—the support of depletion charge beneath the gate—between the gate and the source and drain within an NMOS is known as "charge sharing". In a long–channel NMOS, the gate supports most of the depletion charge beneath it and has dominant control over the channel potential, and must provide most of the electrostatic influence required to reach the threshold condition in the channel, while the source and drain are far enough away that their electrostatic fields support only a small share of the central depletion charge. However, a short-channel NMOS sees both the source and drain having more electrostatic influence, resulting in less gate dominance and less gate voltage being required to reach the threshold condition, as the source and drain now support a larger share of this depletion charge.

This decrease in $L$ results in a reduced $V_T$ as in a short–channel NMOS, the gate has a smaller electrostatic contribution to make before reaching the threshold condition in the channel owing to increased electrostatic influence from the source and drain. As the gate’s contribution is reduced due to increased charge sharing and source and drain electrostatic influence, the required $V_{GS}$ is reduced. Because $V_T$ is the value of $V_{GS}$ at which the threshold condition is reached, $V_T$ is therefore reduced. This is known as threshold-voltage roll-off.

Threshold-voltage roll-off is related to drain-induced barrier lowering (DIBL), as both are manifestations of an underlying loss of electrostatic integrity, but they differ in the variable being changed. $V_T$ roll-off is observed by reducing $L$ while maintaining the same drain-to-source voltage ($V_{DS}$) across otherwise similar devices. DIBL is instead observed by increasing $V_{DS}$ in an NMOS whose length is held constant, causing the drain depletion region to expand, thus increasing the drain’s electrostatic influence and lowering the source–channel barrier. Poorer electrostatic integrity with an already short $L$ gives the drain increased influence at a higher $V_{DS}$, instead of the gate maintaining dominant control. A lower $V_{GS}$ is then needed to reach the threshold condition, which leads to a reduction of the $V_T$. Threshold-voltage roll-off and DIBL therefore share a related electrostatic origin, but roll-off describes the dependence of $V_T$ on $L$, while DIBL describes its dependence on $V_{DS}$.

See also

• Channel length modulation
• Reverse short-channel effect