File:Pre-trigger recording.jpg
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Summary
| Description |
English: Example circuit illustrating how pre-trigger data is recorded using a FIFO. The flash ADC issues one sample per clock, which is stored in the FIFO when RECORD is active. Recording begins when START is asserted and ends upon TRIG. The processor is notified via interrupt (IRQ) that recording has ended, and may then read sample data until the FIFO is empty. |
| Date | |
| Source | Own work |
| Author | Lambtron |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 22:02, 21 April 2026 | | 1,420 × 1,253 (321 KB) | wikimediacommons>Lambtron | Uploaded own work with UploadWizard |
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