English: Cloning a logic gate to split high fanout across multiple copies. By duplicating the gate and redistributing its outputs, the capacitive load seen by each instance is reduced, improving timing. Besides, cloning to isolate downstream high-load sinks. Creating a separate logic copy reduces the capacitive burden on the original gate, allowing better delay optimization along critical paths. These transformations preserve functionality but improve performance by reducing effective output capacitance per gate, and therefore reduce the path delay in circuit.