File:12-input OR gate via NOR and NAND gates.svg
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Size of this PNG preview of this SVG file: 257 × 162 pixels. Other resolutions: 320 × 202 pixels | 640 × 403 pixels | 1,024 × 645 pixels | 1,280 × 807 pixels | 2,560 × 1,614 pixels.
Original file (SVG file, nominally 257 × 162 pixels, file size: 5 KB)
Summary
| Description |
English: An implementation of a cascaded implementation, which used de Morgan's laws to convert or(or(a,b,c),or(d,e,f),or(g,h,i)) into nand(nor(a,b,c),nor(d,e,f),nor(g,h,i)). This is more efficient on logic families such as CMOS, NMOS or TTL where an OR gate needs to be synthesized from a NOR gate and an inverter. |
| Date | |
| Source | Own work |
| Author | Trex4321 |
Licensing
I, the copyright holder of this work, hereby publish it under the following license:
 
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This file is made available under the Creative Commons CC0 1.0 Universal Public Domain Dedication. |
| The person who associated a work with this deed has dedicated the work to the public domain by waiving all of their rights to the work worldwide under copyright law, including all related and neighboring rights, to the extent allowed by law. You can copy, modify, distribute and perform the work, even for commercial purposes, all without asking permission.
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File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 20:26, 4 February 2024 | | 257 × 162 (5 KB) | wikimediacommons>Trex4321 | Uploaded own work with UploadWizard |
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