View source for X86 SIMD instruction listings

{{Short description|List of x86 microprocessor SIMD instructions}}
{{lowercase title|title=x86 SIMD instruction listings}}
{{X86 instruction listings}}

The [[x86]] [[instruction set]] has several times been extended with SIMD ([[Single instruction, multiple data]]) instruction set extensions. These extensions, starting from the [[MMX (instruction set)|MMX]] instruction set extension introduced with [[Pentium MMX]] in 1997, typically define sets of wide registers and instructions that subdivide these registers into fixed-size lanes and perform a computation for each lane in parallel.

== Summary of SIMD extensions ==

The main SIMD instruction set extensions that have been introduced for x86 are:
{| class="wikitable sortable"
! SIMD instruction set extension !! Year !! Description !! Added in
|-
| {{glossary}}{{term|[[MMX (instruction set)|MMX]]}}{{glossary end}}
| 1997
| A set of 57 integer SIMD instruction acting on 64-bit vectors, mostly providing 8/16/32-bit lane-width operations.

Repurposed the old [[x87]] FPU register-file as a bank of eight 64-bit vector registers, referred to as MM0..MM7 when used for MMX instructions. 
| {{nowrap|Intel [[Pentium MMX]],}}<br/>[[AMD K6]],<br/>Intel [[Pentium II]],<br/>{{nowrap|[[Cyrix 6x86]]MX, [[MediaGX]]m,}}<br/>Rise [[mP6]],<br/>IDT [[WinChip]] C6,<br/>[[Transmeta Crusoe]]
|-
| {{glossary}}{{term|SSE}}{{defn|[[Streaming SIMD Extensions]]}}{{glossary end}}
| 1999
| "Katmai New Instructions" - introduced a set of 70 new instructions. Most but not all of these instructions provide scalar and vector operations on 32-bit floating-point values in 128-bit SIMD vector registers. (Some of the SSE instructions were instead new MMX instructions and non-SIMD instructions such as <code>SFENCE</code> - the subset of SSE that excludes the 128-bit SIMD register instructions is known as "MMX+", and is supported on some AMD processors that didn't implement full SSE, notably early [[Athlon]]s and [[Geode LX]].)

SSE introduced a new set of eight vector registers XMM0..XMM7, each 128 bits, and a status/control register MXCSR.

This set of eight vector registers would later be extended to 16 registers with the introduction of [[x86-64]].
| Intel [[Pentium III]],<br/>AMD [[Athlon XP]],<br/>[[VIA C3]] "Nehemiah",<br/>[[Transmeta Efficeon]]
|-
| {{glossary}}{{term|[[SSE2]]}}{{defn|Streaming SIMD Extensions 2}}{{glossary end}}
| 2000
| Extended SSE with 144 new instructions - mainly additional instructions to work on scalars and vectors of 64-bit floating-point values, as well as 128-bit-vector forms of most of the MMX integer instructions.
| Intel [[Pentium 4]],<br/>Intel [[Pentium M]],<br/>AMD [[Athlon 64]],<br/>[[Transmeta Efficeon]],<br/>[[VIA C7]]
|-
| {{glossary}}{{term|[[SSE3]]}}{{defn|Streaming SIMD Extensions 3}}{{glossary end}}
| 2004
| "Prescott New Instructions": added a set of 13 new instructions,{{efn|The count of 13 instructions for SSE3 includes the non-SIMD instructions <code>MONITOR</code> and <code>MWAIT</code> that were also introduced as part of "Prescott New Instructions" - these two instructions are considered to be SSE3 instructions by Intel but not by AMD.}} mostly horizontal add/subtract operations.
| [[Pentium 4#Prescott|Intel Pentium 4 "Prescott"]],<br/>[[Transmeta Efficeon]] 8800,<br/>[[Athlon 64|Athlon 64 "Venice"]],<br/>[[VIA C7]],<br/>[[Yonah (microprocessor)|Intel Core "Yonah"]]
|-
| {{glossary}}{{term|[[SSSE3]]}}{{defn|Supplemental SSE3}}{{glossary end}}
| 2006
| Added a set of 32 new instructions to extend MMX and SSE, including a byte-shuffle instruction.
| [[Intel Core 2|Intel Core 2 "Merom"]],<br/>[[VIA Nano]] 2000,<br/>[[Bonnell (microarchitecture)|Intel Atom "Bonnell"]],<br/>[[Bobcat (microarchitecture)|AMD "Bobcat"]],<br/>[[Bulldozer (microarchitecture)|AMD FX "Bulldozer"]]
|-
| {{glossary}}{{term|SSE4a}}{{glossary end}}
| 2007
| AMD-only extension that added a set of 4 instructions, including bitfield insert/extract and scalar non-temporal store instructions.
| [[AMD K10]]
|-
| {{glossary}}{{term|[[SSE4.1]]}}{{glossary end}}
| 2007
| Added a set of 47 instructions, including variants of integer min/max, widening integer conversions, vector lane insert/extract, and dot-product instructions. 
| [[Penryn (microarchitecture)|Intel Core 2 "Penryn"]],<br/>[[VIA Nano]] 3000,<br/>[[Bulldozer (microarchitecture)|AMD FX "Bulldozer"]],<br/>[[Jaguar (microarchitecture)|AMD "Jaguar"]],<br/>[[Silvermont|Intel Atom "Silvermont"]]
|-
| {{glossary}}{{term|[[SSE4.2]]}}{{glossary end}}
| 2008
| Added a set of 7 instructions, mostly pertaining to string processing.
| [[Nehalem (microarchitecture)|Intel Core i7 "Nehalem"]],<br/>[[Bulldozer (microarchitecture)|AMD FX "Bulldozer"]],<br/>[[Jaguar (microarchitecture)|AMD "Jaguar"]],<br/>[[Silvermont|Intel Atom "Silvermont"]],<br/>[[VIA Nano]] QuadCore C4000
|-
| {{glossary}}{{term|AVX}}{{defn|[[Advanced Vector Extensions]]}}{{glossary end}}
| 2011
| Extended the XMM0..XMM15 vector registers to 256-bit registers, referred to as YMM0..YMM15 when used as full 256-bit registers.

Added three-operand variants of most of the SSE1-4 vector instructions, as well as 256-bit vector variants of most of the SSE1-4 vector instructions acting on 32/64-bit floating-point values. These new instruction variants are all encoded with the new [[VEX prefix]].
| [[Sandy Bridge|Intel Core i7 "Sandy Bridge"]],<br/>[[Bulldozer (microarchitecture)|AMD FX "Bulldozer"]],<br/>[[Jaguar (microarchitecture)|AMD "Jaguar"]],<br/>[[VIA Nano]] QuadCore C4000
|-
| {{glossary}}{{term|FMA3}}{{defn|[[FMA instruction set|Fused Multiply-Add]]}}{{glossary end}}
| 2013
| Added three-operand floating-point fused-multiply add operations, scalar and vector variants.
| [[Haswell (microarchitecture)|Intel Core i7 "Haswell"]],<br/>[[Piledriver (microarchitecture)|AMD FX "Piledriver"]],<br/>[[Zhaoxin]] Yongfeng
|-
| {{glossary}}{{term|AVX2}}{{defn|Advanced Vector Extensions 2}}{{glossary end}}
| 2013
| Added 256-bit vector variants of most of the MMX/SSE1-4 vector integer instructions. Also adds vector gather instructions.
| [[Haswell (microarchitecture)|Intel Core i7 "Haswell"]],<br/>[[Excavator (microarchitecture)|AMD FX "Excavator"]],<br/>[[VIA Nano]] QuadCore C4000
|-
| {{glossary}}{{term|[[AVX-512]]}}{{glossary end}}
| 2016
| Extended the YMM0..YMM15 vector registers to a set of 32 registers, each 512-bits wide - referred to as ZMM0..ZMM31 when used as 512-bit registers. Also added eight opmask registers K0..K7.

Added 512-bit versions of most of the MMX/SSE/AVX vector instructions, as well as a substantial number of additional instructions. These are mostly encoded with the new [[EVEX prefix]] (except for opmask management instructions, which continue to use the [[VEX prefix]].)

Added the ability to perform per-vector-lane masking of the operation of most of its vector instructions, by using the opmask registers. Also added embedded rounding controls for floating-point instructions and a scalar-to-vector broadcast function for most instructions that can accept memory operands.
| {{glossary}}{{term|AVX512 Foundation:}}{{defn|[[Xeon Phi|Intel Xeon Phi x200]],<br/>[[Skylake (microarchitecture)|Intel Core i9 "Skylake-X"]],<br/>AMD [[Zen 4]]}}{{glossary end}}

(See [[AVX-512#New instructions by sets]] for additional subsets.)
|-
| {{glossary}}{{term|AMX}}{{defn|[[Advanced Matrix Extensions]]}}{{glossary end}}
| 2023
| Added a set of eight new tile registers, referred to as TMM0..TMM7. Each of these tile registers has a size of 8192 bits (16 rows of 64 bytes each). Also added instructions to perform [[matrix multiplication]] on these registers with various data formats.
| {{nowrap|[[Sapphire Rapids|Intel Xeon "Sapphire Rapids"]]}}
|-
| {{glossary}}{{term|AVX10.1}}{{glossary end}}
| 2024
| Reformulation of AVX-512 that includes most of the optional AVX-512 subsets as baseline functionality, but also allows for implementations to reduce their maximum supported vector-register width to 256 bits.
| [[Granite Rapids|Intel Xeon 6 "Granite Rapids"]]
|-
| {{glossary}}{{term|AVX10.2}}{{glossary end}}
| (2025)
| Adds support for rounding modifiers for 256-bit floating-point numbers, as well as a handful of added instructions.
| (Intel [[Diamond Rapids]])
|}
{{notelist}}
{{vpad}}



== MMX instructions and extended variants thereof ==

These instructions are, unless otherwise noted, available in the following forms:
* MMX: 64-bit vectors, operating on mm0..mm7 registers (aliased on top of the old x87 register file)
* SSE2: 128-bit vectors, operating on xmm0..xmm15 registers (xmm0..xmm7 in 32-bit mode)
* AVX: 128-bit vectors, operating on xmm0..xmm15 registers, with a new three-operand encoding enabled by the new [[VEX prefix]]. (AVX introduced 256-bit vector registers, but the full width of these vectors was in general not made available for integer SIMD instructions until AVX2.) 
* AVX2: 256-bit vectors, operating on ymm0..ymm15 registers (extended versions of the xmm0..xmm15 registers)
* AVX-512: 512-bit vectors, operating on zmm0..zmm31 registers (zmm0..zmm15 are extended versions of the ymm0..ymm15 registers, while zmm16..zmm31 are new to AVX-512). AVX-512 also introduces opmasks, allowing the operation of most instructions to be masked on a per-lane basis by an opmask register (the lane width varies from one instruction to another). AVX-512 also adds broadcast functionality for many of its instructions - this is used with memory source arguments to replicate a single value to all lanes of a vector calculation. The tables below provide indications of whether opmasks and broadcasts are supported for each instruction, and if so, what lane-widths they are using.

For many of the instruction mnemonics, <code>(V)</code> is used to indicate that the instruction mnemonic exists in forms with and without a leading V - the form with the leading V is used for the VEX/EVEX-prefixed instruction variants introduced by AVX/AVX2/AVX-512, while the form without the leading V is used for legacy MMX/SSE encodings without VEX/EVEX-prefix.

=== Original Pentium MMX instructions, and SSE2/AVX/AVX-512 extended variants thereof ===
{| class="wikitable"
! rowspan=2 colspan=2 | Description
! rowspan=2 | Instruction mnemonics
! rowspan=2 | Basic opcode
! rowspan=2 | MMX<br>(no prefix)
! rowspan=2 | SSE2<br>(66h prefix)
! rowspan=2 | AVX<br>(VEX.66 prefix)
! colspan=4 | AVX-512 (EVEX.66 prefix)
|-
! supported !! subset !! lane !! bcst
|-
| colspan=2 | Empty MMX technology state. (MMX)

Mark all the FP/MMX registers as Empty, so that they can be freely used by later x87 code.
| <code>EMMS</code> (MMX)
| rowspan=3 | <code>0F 77</code>
| rowspan=3 {{yes|<code>EMMS</code>}}
| rowspan=3 {{no}}
| rowspan=3 {{yes|{{resize|85%|<code>VZEROUPPER</code>(L{{=}}0)<br><code>VZEROALL</code>(L{{=}}1)}}<br>{{efn|For code that may potentially mix use of legacy-SSE instructions with AVX instructions, it is strongly recommended to execute a <code>VZEROUPPER</code> or <code>VZEROALL</code> instruction after executing AVX instructions but before executing SSE instructions. If this is not done, any subsequent legacy-SSE code may be subject to severe performance degradation.<ref>Intel, [https://www.intel.com/content/dam/develop/external/us/en/documents/11mc12-avoiding-2bavx-sse-2btransition-2bpenalties-2brh-2bfinal-809104.pdf Avoiding AVX-SSE Transition Penalties], see section 3.3. [https://web.archive.org/web/20240920151523/https://www.intel.com/content/dam/develop/external/us/en/documents/11mc12-avoiding-2bavx-sse-2btransition-2bpenalties-2brh-2bfinal-809104.pdf Archived] on Sep 20, 2024.</ref>}}}}{{efn|1=On some early AVX implementations (e.g. [[Sandy Bridge]]<ref>Intel, [https://web.archive.org/web/20170706071646/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-desktop-specification-update.pdf 2nd Generation Intel Core Processor Family Desktop Specification Update], order no. 324643-037, apr 2016, see erratum BJ49 on page 36. Archived from the [https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-desktop-specification-update.pdf original] on 6 Jul 2017.</ref>) encoding the <code>VZEROUPPER</code> and <code>VZEROALL</code> instructions with VEX.W=1 will result in #UD - for this reason, it is recommended to encode these instructions with VEX.W=0.}}
| rowspan=3 {{no}}
| rowspan=3 {{n/a}}
| rowspan=3 {{n/a}}
| rowspan=3 {{n/a}}
|-
| colspan=2 | Zero out upper bits of vector registers <code>YMM0</code> to <code>YMM15</code> (AVX) || <code>VZEROUPPER</code> (AVX)
|-
| colspan=2 | Zero out all bits of vector registers <code>YMM0</code> to <code>YMM15</code> (AVX) || <code>VZEROALL</code> (AVX)
|-
! colspan=11 |
|-
| rowspan=2 | Move scalar value from GPR (general-purpose register) or memory to vector register, with zero-fill 
| 32-bit || <code>(V)MOVD mm, r/m32</code> || rowspan=2 | <code>0F 6E /r</code> || {{yes}}||{{yes}}||{{yes|Yes (L{{=}}0,W{{=}}0)}}||{{yes|Yes (L{{=}}0,W{{=}}0)}}||F ||{{no}}||{{no}}
|-
| 64-bit<br/>(x86-64) || <code>(V)MOVQ mm, r/m64</code>,<br/><code>MOVD mm, r/m64</code>{{efn|name="mmx_movq"|The 64-bit move instruction forms that are encoded by using a <code>REX.W</code> prefix with the {{nowrap|<code>0F 6E</code>}} and {{nowrap|<code>0F 7E</code>}} opcodes are listed with different mnemonics in Intel and AMD documentation — <code>MOVQ</code> in Intel documentation<ref>Intel, [https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Intel 64 and IA-32 Architectures Software Developer’s Manual] order no. 325462-086, December 2024, Volume 2B, MOVD/MOVQ instruction entry, page 1289. [https://web.archive.org/web/20241230194917/https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Archived] on 30 Dec 2024.</ref> and <code>MOVD</code> in AMD documentation.<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf AMD64 Architecture Programmer’s Manual Volumes 1–5], pub.no. 40332, rev 4.08, April 2024, see entries for <code>MOVD</code> instruction on pages 2159 and 3040. [https://web.archive.org/web/20250119235947/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf Archived] on 19 Jan 2025.</ref><br/>This is a documentation difference only — the operation performed by these opcodes is the same for Intel and AMD.<br/>This documentation difference applies only to the MMX/SSE forms of these opcodes — for VEX/EVEX-encoded forms, both Intel and AMD use the mnemonic <code>VMOVQ</code>.)}} || {{yes|Yes<br/>(REX.W)}}||{{yes|Yes<br/>(REX.W){{efn|name="sse_movq"|The REX.W-encoded variants of <code>MOVQ</code> are available in 64-bit "long mode" only. For SSE2 and later, <code>MOVQ</code> to and from xmm/ymm/zmm registers can also be encoded with {{nowrap|<code>F3 0F 7E /r</code>}} and {{nowrap|<code>66 0F D6 /r</code>}} respectively - these encodings are shorter and available outside 64-bit mode.}}}}||{{yes|Yes (L{{=}}0,W{{=}}1)}}||{{yes|Yes (L{{=}}0,W{{=}}1)}}||F || {{no}} || {{no}}
|-
| rowspan=2 | Move scalar value from vector register to GPR or memory
| 32-bit || <code>(V)MOVD r/m32, mm</code> || rowspan=2 | <code>0F 7E /r</code> || {{yes}}||{{yes}}||{{yes|Yes (L{{=}}0,W{{=}}0)}}||{{yes|Yes (L{{=}}0,W{{=}}0)}}||F ||{{no}}||{{no}}
|-
| 64-bit<br/>(x86-64) || <code>(V)MOVQ r/m64, mm</code>,<br/><code>MOVD r/m64, mm</code>{{efn|name="mmx_movq"}} || {{yes|Yes<br/>(REX.W)}} || {{yes|Yes<br/>(REX.W){{efn|name="sse_movq"}}}} || {{yes|Yes (L{{=}}0,W{{=}}1)}}||{{yes|Yes (L{{=}}0,W{{=}}1)}}||F || {{no}} || {{no}}
|-
| rowspan=4 colspan=2 | Vector move between vector register and either memory or another vector register.

For move to/from memory, the memory address is required to be aligned for <code>(V)MOVDQA</code> variants but not for <code>MOVQ</code>.

128-bit VEX-encoded form of <code>VMOVDQA</code> with memory argument will, if the memory is cacheable, perform its memory access atomically.{{efn|name="atomic_vmovdqa"|1=On all Intel,<ref>Intel, [https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Intel 64 and IA-32 Architectures Software Developer’s Manual] order no. 325462-086, December 2024, Volume 3B section 10.1.1, page 3368. [https://web.archive.org/web/20241230194917/https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Archived] on 30 Dec 2024.</ref> AMD<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf AMD64 Architecture Programmer’s Manual Volumes 1–5], pub.no. 40332, rev 4.08, April 2024, Volume 2, section 7.3.2 on page 650. [https://web.archive.org/web/20250119235947/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf Archived] on 19 Jan 2025.</ref> and Zhaoxin<ref>GCC Bugzilla, [https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c34 Bug 104688 - gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX], see comments 34 and 38 for a statement from Zhaoxin on <code>VMOVDQA</code> atomicity. [https://web.archive.org/web/20241212232805/https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 Archived] on 12 Dec 2024.</ref> processors that support AVX, the 128-bit forms of <code>VMOVDQA</code> (encoded with a VEX prefix and VEX.L=0) are, when used with a memory argument addressing WB (write-back cacheable) memory, architecturally guaranteed to perform the 128-bit memory access atomically - this applies to both load and store.<p>(Intel and AMD provide somewhat wider guarantees covering more 128-bit instruction variants, but Zhaoxin provides the guarantee for cacheable <code>VMOVDQA</code> only.)<p>On processors that support SSE but don't support AVX, the 128-bit forms of SSE load/store instructions such as <code>MOVAPS</code>/<code>MOVAPD</code>/<code>MOVDQA</code> are ''not'' guaranteed to execute atomically — examples of processors where such instructions have been observed to execute non-atomically include Intel [[Yonah (microprocessor)|Core Duo]] and [[AMD K10]].<ref>Stack Overflow, [https://stackoverflow.com/questions/7646018/sse-instructions-which-cpus-can-do-atomic-16b-memory-operations SSE instructions: which CPUs can do atomic 16B memory operations?] [https://web.archive.org/web/20240930173924/https://stackoverflow.com/questions/7646018/sse-instructions-which-cpus-can-do-atomic-16b-memory-operations Archived] on 30 Sep 2024.</ref>}}
| rowspan=2 | {{nowrap|<code>MOVQ mm/m64, mm</code>}}(MMX)<br>{{nowrap|<code>(V)MOVDQA xmm/m128,xmm</code>}}
| rowspan=2 | <code>0F 7F /r</code>
| rowspan=2 {{yes|<code>MOVQ</code>}}
| rowspan=2 {{yes|<code>MOVDQA</code>}}
| rowspan=2 {{yes|<code>VMOVDQA</code>{{zwsp}}{{efn|name="vmovdqa_avx1"|<code>VMOVDQA</code> is available with a vector length of 256 bits under AVX, not requiring AVX2.}}}}
| {{yes|<code>VMOVDQA32</code>{{zwsp}}(W0)}} || F || 32 || {{no}}
|-
| {{yes|<code>VMOVDQA64</code>{{zwsp}}(W1)}} || F || 64 || {{no}}
|-
| rowspan=2 | <code>MOVQ mm, mm/m64</code>(MMX)<br><code>(V)MOVDQA xmm,xmm/m128</code>
| rowspan=2 | <code>0F 6F /r</code>
| rowspan=2 {{yes|<code>MOVQ</code>}}
| rowspan=2 {{yes|<code>MOVDQA</code>}}
| rowspan=2 {{yes|<code>VMOVDQA</code>{{zwsp}}{{efn|name="vmovdqa_avx1"}}}}
| {{yes|<code>VMOVDQA32</code>{{zwsp}}(W0)}} || F || 32 || {{no}}
|-
| {{yes|<code>VMOVDQA64</code>{{zwsp}}(W1)}} || F || 64 || {{no}}
|-
! colspan=11 |
|-
| colspan=2 | Pack 32-bit signed integers to 16-bit, with saturation || {{nowrap|<code>(V)PACKSSDW mm, mm/m64</code>}}{{zwsp}}{{efn|name="mmx_lane128"|For the <code>VPACK*</code> and <code>VPUNPCK*</code> instructions, encodings with a vector-length wider than 128 bits are available under AVX2 and AVX-512, but the operation of such encodings is split into 128-bit lanes where each 128-bit lane internally performs the same operation as the 128-bit variant of the instruction.}} || <code>0F 6B /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||BW||16||32
|-
| colspan=2 | Pack 16-bit signed integers to 8-bit, with saturation || <code>(V)PACKSSWB mm, mm/m64</code>{{zwsp}}{{efn|name="mmx_lane128"}} || <code>0F 63 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| colspan=2 | Pack 16-bit unsigned integers to 8-bit, with saturation || <code>(V)PACKUSWB mm, mm/m64</code>{{zwsp}}{{efn|name="mmx_lane128"}} || <code>0F 67 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| rowspan=3 | Unpack and interleave packed integers from the high halves of two input vectors

| 8-bit || {{nowrap|<code>(V)PUNPCKHBW mm, mm/m64</code>}}{{zwsp}}{{efn|name="mmx_lane128"}} || <code>0F 68 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || {{nowrap|<code>(V)PUNPCKHWD mm, mm/m64</code>}}{{zwsp}}{{efn|name="mmx_lane128"}} || <code>0F 69 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| {{nowrap|32-bit}} || {{nowrap|<code>(V)PUNPCKHDQ mm, mm/m64</code>}}{{zwsp}}{{efn|name="mmx_lane128"}} || <code>0F 6A /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| rowspan=3 | Unpack and interleave packed integers from the low halves of two input vectors
| 8-bit || {{nowrap|<code>(V)PUNPCKLBW mm, mm/m32</code>}}{{zwsp}}{{efn|name="mmx_lane128"}}{{efn|name="mmx_unpck"|For the memory argument forms of <code>(V)PUNPCKL*</code> instructions, the memory argument is half-width only for the MMX variants of the instructions. For SSE/AVX/AVX-512 variants, the width of the memory argument is the full vector width even though only half of it is actually used.}}|| <code>0F 60 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || {{nowrap|<code>(V)PUNPCKLWD mm, mm/m32</code>}}{{zwsp}}{{efn|name="mmx_lane128"}}{{efn|name="mmx_unpck"}} || <code>0F 61 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 32-bit || {{nowrap|<code>(V)PUNPCKLDQ mm, mm/m32</code>}}{{zwsp}}{{efn|name="mmx_lane128"}}{{efn|name="mmx_unpck"}} || <code>0F 62 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
! colspan=11 |
|-
| rowspan=3 | Add packed integers
| 8-bit || <code>(V)PADDB mm, mm/m64</code> || <code>0F FC /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PADDW mm, mm/m64</code> || <code>0F FD /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 32-bit || <code>(V)PADDD mm, mm/m64</code> || <code>0F FE /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| rowspan=2 | Add packed signed integers with saturation
| 8-bit || <code>(V)PADDSB mm, mm/m64</code> || <code>0F EC /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PADDSW mm, mm/m64</code> || <code>0F ED /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | Add packed unsigned integers with saturation
| 8-bit || <code>(V)PADDUSB mm, mm/m64</code> || <code>0F DC /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PADDUSW mm, mm/m64</code> || <code>0F DD /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
! colspan=11 |
|-
| rowspan=3 | Subtract packed integers
| 8-bit || <code>(V)PSUBB mm, mm/m64</code> || <code>0F F8 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PSUBW mm, mm/m64</code> || <code>0F F9 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 32-bit || <code>(V)PSUBD mm, mm/m64</code> || <code>0F FA /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| rowspan=2 | Subtract packed signed integers with saturation
| 8-bit || <code>(V)PSUBSB mm, mm/m64</code> || <code>0F E8 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PSUBSW mm, mm/m64</code> || <code>0F E9 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | Subtract packed unsigned integers with saturation
| 8-bit || <code>(V)PSUBUSB mm, mm/m64</code> || <code>0F D8 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PSUBUSW mm, mm/m64</code> || <code>0F D9 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
! colspan=11 |
|-
| rowspan=3 | Compare packed integers for equality
| 8-bit || <code>(V)PCMPEQB mm, mm/m64</code> || <code>0F 74 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|name="pcmp512"|The EVEX-encoded variants of the <code>VPCMPEQ*</code> and <code>VPCMPGT*</code> instructions write their results to AVX-512 opmask registers. This differs from the older non-EVEX variants, which write comparison results as vectors of all-0s/all-1s values to the regular mm/xmm/ymm vector registers.}}}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PCMPEQW mm, mm/m64</code> || <code>0F 75 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|name="pcmp512"}}}}||BW||16||{{no}}
|-
| 32-bit || <code>(V)PCMPEQD mm, mm/m64</code> || <code>0F 76 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0){{efn|name="pcmp512"}}}}||F||32||32
|-
| rowspan=3 | Compare packed integers for signed greater-than
| 8-bit || <code>(V)PCMPGTB mm, mm/m64</code> || <code>0F 64 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|name="pcmp512"}}}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PCMPGTW mm, mm/m64</code> || <code>0F 65 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|name="pcmp512"}}}}||BW||16||{{no}}
|-
| 32-bit || <code>(V)PCMPGTD mm, mm/m64</code> || <code>0F 66 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0){{efn|name="pcmp512"}}}}||F||32||32
|-
! colspan=11 |
|-
| colspan=2 | Multiply packed 16-bit signed integers, add results pairwise into 32-bit integers || <code>(V)PMADDWD mm, mm/m64</code> || <code>0F F5 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|name="mmx_pmadd512"|The <code>(V)PMADDWD</code> instruction will add multiplication results pairwise, but will not add the sum to an accumulator. AVX512_VNNI provides the instructions <code>VDPWSSD</code> and <code>WDPWSSDS</code>, which will add multiplication results pairwise, and then also add them to a per-32-bit-lane accumulator.}}}}||BW||32||{{no}}
|-
| colspan=2 | Multiply packed 16-bit signed integers, store high 16 bits of results || <code>(V)PMULHW mm, mm/m64</code> || <code>0F E5 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| colspan=2 | Multiply packed 16-bit integers, store low 16 bits of results || <code>(V)PMULLW mm, mm/m64</code> || <code>0F D5 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
! colspan=11 |
|-
| rowspan=2 colspan=2 | Vector [[Bitwise operation#AND|bitwise AND]] || rowspan=2 | <code>(V)PAND mm, mm/m64</code> || rowspan=2 | <code>0F DB /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || rowspan=2 {{yes}}
| {{yes|<code>VPANDD</code>{{zwsp}}(W0)}} || F || 32 || 32
|-
| {{yes|<code>VPANDQ</code>{{zwsp}}(W1)}} || F || 64 || 64
|-
| rowspan=2 colspan=2 | Vector bitwise AND-NOT || rowspan=2 | <code>(V)PANDN mm, mm/m64</code> || rowspan=2 | <code>0F DF /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || rowspan=2 {{yes}}
| {{yes|<code>VPANDND</code>{{zwsp}}(W0)}} || F || 32 || 32
|-
| {{yes|<code>VPANDNQ</code>{{zwsp}}(W1)}} || F || 64 || 64
|-
| rowspan=2 colspan=2 | Vector [[Bitwise operation#OR|bitwise OR]] || rowspan=2 | <code>(V)POR mm, mm/m64</code> || rowspan=2 | <code>0F EB /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || rowspan=2 {{yes}}
| {{yes|<code>VPORD</code>(W0)}} || F || 32 || 32
|-
| {{yes|<code>VPORQ</code>(W1)}} || F || 64 || 64
|-
| rowspan=2 colspan=2 | Vector [[Bitwise operation#XOR|bitwise XOR]] || rowspan=2 | <code>(V)PXOR mm, mm/m64</code> || rowspan=2 | <code>0F EE /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || rowspan=2 {{yes}}
| {{yes|<code>VPXORD</code>(W0)}} || F || 32 || 32
|-
| {{yes|<code>VPXORQ</code>(W1)}} || F || 64 || 64
|-
! colspan=11 |
|-
| rowspan=6 | [[Logical shift|left-shift of packed integers]], with common shift-amount
| rowspan=2 | 16-bit || <code>(V)PSLLW mm, imm8</code> || <code>0F 71 /6 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| <code>(V)PSLLW mm, mm/m64</code>{{efn|name=mmx_shift|text=For the MMX packed shift instructions <code>PSLL*</code> and <code>PSR*</code> with a shift-argument taken from a vector source (mm or m64), the shift-amount is considered to be a single 64-bit scalar value - the same shift-amount is used for all lanes of the destination vector. This shift-amount is unsigned and is not masked - all bits are considered (e.g. a shift-amount of <code>0x80000000_00000000</code> can be specified and will have the same effect as a shift-amount of 64).<p>For all SSE2/AVX/AVX512 extended variants of these instructions, the shift-amount vector argument is considered to be a 128-bit (xmm or m128) argument - the bottom 64 bits are used as the shift-amount.<p>Packed shift-instructions that can take a variable per-lane shift-amount were introduced in AVX2 for 32/64-bit lanes and AVX512BW for 16-bit lanes (<code>VPSLLV*</code>, <code>VPSRLV*</code>, <code>VPSRAV*</code> instructions).</p>}} || <code>0F F1 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | 32-bit || <code>(V)PSLLD mm, imm8</code> || {{nowrap|<code>0F 72 /6 ib</code>}} || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| <code>(V)PSLLD mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F F2 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||{{no}}
|-
| rowspan=2 | 64-bit || <code>(V)PSLLQ mm, imm8</code> || {{nowrap|<code>0F 73 /6 ib</code>}} || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| <code>(V)PSLLQ mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F F3 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||{{no}}
|-
| rowspan=4 | [[Arithmetic shift|Right-shift of packed signed integers]], with common shift-amount
| rowspan=2 | 16-bit || <code>(V)PSRAW mm, imm8</code> || <code>0F 71 /4 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| <code>(V)PSRAW mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F E1 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | 32-bit || <code>(V)PSRAD mm, imm8</code> || <code>0F 72 /4 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| <code>(V)PSRAD mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F E2 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||{{no}}
|-
| rowspan=6 | [[Logical shift|Right-shift of packed unsigned integers]], with common shift-amount
| rowspan=2 | 16-bit || <code>(V)PSRLW mm, imm8</code> || <code>0F 71 /2 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| <code>(V)PSRLW mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F D1 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | 32-bit || <code>(V)PSRLD mm, imm8</code> || <code>0F 72 /2 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||32
|-
| <code>(V)PSRLD mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F D2 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||32||{{no}}
|-
| rowspan=2 | {{nowrap|64-bit}} || <code>(V)PSRLQ mm, imm8</code> || <code>0F 73 /2 ib</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| <code>(V)PSRLQ mm, mm/m64</code>{{efn|name=mmx_shift}} || <code>0F D3 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||{{no}}
|-
|}
{{notelist}}
{{vpad}}

=== MMX instructions added with MMX+/SSE/SSE2/SSSE3, and SSE2/AVX/AVX-512 extended variants thereof ===

{| class="wikitable"
! rowspan=2 colspan=2 | Description
! rowspan=2 | Instruction mnemonics
! rowspan=2 | Basic opcode
! rowspan=2 | MMX<br>(no prefix)
! rowspan=2 | SSE2<br>(66h prefix)
! rowspan=2 | AVX<br>(VEX.66 prefix)
! colspan=4 | AVX-512 (EVEX.66 prefix)
|-
! supported !! subset !! lane !! bcst
|-
! colspan=11 | Added with SSE and MMX+
|-
| colspan=2 | Perform shuffle of four 16-bit integers in 64-bit vector (MMX){{efn|For shuffle of four 16-bit integers in a 64-bit section of a 128-bit XMM register, the SSE2 instructions <code>PSHUFLW</code> (opcode {{nowrap|<code>F2 0F 70 /r</code>}}) or <code>PSHUFHW</code> (opcode {{nowrap|<code>F3 0F 70 /r</code>}}) may be used.}} 
| {{nowrap|<code>PSHUFW mm,mm/m64,imm8</code>(MMX)}}|| rowspan=2 | <code>0F 70 /r ib</code> || rowspan=2 {{yes|<code>PSHUFW</code>}} || rowspan=2 {{yes|<code>PSHUFD</code>}} || rowspan=2 {{yes|<code>VPSHUFD</code>}} || rowspan=2 {{yes|<code>VPSHUFD</code><br/>(W{{=}}0)}} || rowspan=2 | F || rowspan=2 | 32 || rowspan=2 | 32
|-
| colspan=2 | Perform shuffle of four 32-bit integers in 128-bit vector (SSE2)
| {{nowrap|<code>(V)PSHUFD xmm,xmm/m128,imm8</code>{{efn|name="mmx2_lane128"|For the <code>VPSHUFD</code>, <code>VPSHUFB</code>, <code>VPHADD*</code>, <code>VPHSUB*</code> and <code>VPALIGNR</code> instructions, encodings with a vector-length wider than 128 bits are available under AVX2 and/or AVX-512, but the operation of such encodings is split into 128-bit lanes where each 128-bit lane internally performs the same operation as the 128-bit variant of the instruction.}}}}
|-
| colspan=2 | Insert integer into 16-bit vector register lane
| <code>(V)PINSRW mm,r32/m16,imm8</code> || <code>0F C4 /r ib</code> || {{yes}}||{{yes}}|| {{yes|Yes (L{{=}}0,W{{=}}0{{efn|name=vlane16_w0|For the VEX-encoded forms of the <code>VPINSRW</code> and <code>VPEXTRW</code> instruction, the Intel SDM (as of rev 084) indicates that the instructions must be encoded with VEX.W{{=}}0, however neither Intel XED nor AMD APM indicate any such requirement.}})}} || {{yes|Yes (L{{=}}0)}} || BW || {{no}} || {{no}}
|-
| colspan=2 | Extract integer from 16-bit vector register lane, with zero-extension
| <code>(V)PEXTRW r32,mm,imm8</code>{{efn|name="pextrw"|The {{nowrap|<code>0F C5 /r ib</code>}} variant of <code>PEXTRW</code> allows register destination only. For SSE4.1 and later, a variant that allows a memory destination is available with the opcode {{nowrap|<code>66 0F 3A 15 /r ib</code>.}}}} || <code>0F C5 /r ib</code> || {{yes}}||{{yes}}|| {{yes|Yes (L{{=}}0,W{{=}}0{{efn|name=vlane16_w0}})}} || {{yes|Yes (L{{=}}0)}} || BW || {{no}} || {{no}}
|-
| colspan=2 | Create a bitmask made from the top bit of each byte in the source vector, and store to integer register
| <code>(V)PMOVMSKB r32,mm</code> || <code>0F D7 /r</code> || {{yes}} || {{yes}} || {{yes}} || {{no|No{{efn|EVEX-prefixed opcode not available. Under AVX-512, a bitmask made from the top bit of each byte can instead be constructed with the <code>VPMOVB2M</code> instruction, with opcode {{nowrap|<code>EVEX.F3.0F38.W0 29 /r</code>}}, which will store such a bitmask to an opmask register.}}}} ||{{n/a}}||{{n/a}}||{{n/a}} 
|-
| colspan=2 | Minimum-value of packed unsigned 8-bit integers || <code>(V)PMINUB mm,mm/m64</code> || <code>0F DA /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| colspan=2 | Maximum-value of packed unsigned 8-bit integers || <code>(V)PMAXUB mm,mm/m64</code> || <code>0F DE /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| colspan=2 | Minimum-value of packed signed 16-bit integers || <code>(V)PMINSW mm,mm/m64</code> || <code>0F EA /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| colspan=2 | Maximum-value of packed signed 16-bit integers  || <code>(V)PMAXSW mm,mm/m64</code> || <code>0F EE /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan = 2 | Rounded average of packed unsigned integers. The per-lane operation is:<br/><code>dst ← (src1 + src2 + 1)>>1</code>
| 8-bit || <code>(V)PAVGB mm,mm/m64</code> || <code>0F E0 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PAVGW mm,mm/m64</code> || <code>0F E3 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| colspan=2 | Multiply packed 16-bit unsigned integers, store high 16 bits of results  || <code>(V)PMULHUW mm,mm/mm64</code> || <code>0F E4 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| colspan=2 | Store vector register to memory using Non-Temporal Hint.<p>Memory operand required to be aligned for all <code>(V)MOVNTDQ</code> variants, but not for <code>MOVNTQ</code>.</p> || <code>MOVNTQ m64,mm</code>(MMX)<br><code>(V)MOVNTDQ m128,xmm</code> || <code>0F E7 /r</code> || {{yes|<code>MOVNTQ</code>}} || {{yes|<code>MOVNTDQ</code>}} || {{yes|<code>VMOVNTDQ</code>{{efn|name="mmx2_mov256"|<code>VMOVNTDQ</code> is available with a vector length of 256 bits under AVX, not requiring AVX2.}}}}<!-- The Intel SDM entry for MOVNTDQ describes that the instructions must be encoded with VEX.L=0, but lists both 256-bit and 512-bit variants, and XED accepts C5 FD E7 00 as a valid VEX.L=1 encoding of the instruction--> || {{yes|<code>VMOVNTDQ</code><br/>(W{{=}}0)}} || F || {{no}} || {{no}}
|-
| colspan=2 | Compute sum of absolute differences for eight 8-bit unsigned integers, storing the result as a 64-bit integer.<p>For vector widths wider than 64 bits (SSE/AVX/AVX-512), this calculation is done separately for each 64-bit lane of the vectors, producing a vector of 64-bit integers.</p> || <code>(V)PSADBW mm,mm/m64</code> || <code>0F F6 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||{{no}}||{{no}}
|-
| colspan=2 | Unaligned store vector register to memory using byte write-mask, with Non-Temporal Hint.<p>First argument provides data to store, second argument provides byte write-mask (top bit of each byte).{{efn|For the <code>MASKMOVQ</code> and <code>(V)MASKMOVDQU</code> instructions, exception and trap behavior for disabled lanes is implementation-dependent. For example, a given implementation may signal a data breakpoint or a page fault for bytes that are zero-masked and not actually written.}} Address to store to is given by DS:DI/EDI/RDI (DS: segment overridable with segment-prefix).</p> || <code>MASKMOVQ mm,mm</code>(MMX)<br/>{{nowrap|<code>(V)MASKMOVDQU xmm,xmm</code>}} || <code>0F F7 /r</code> || {{yes|{{resize|85%|<code>MASKMOVQ</code>}}}} || {{yes|{{resize|85%|<code>MASKMOVDQU</code>}}}}<!-- The Intel SDM describes the instruction as allowing unaligned accesses even for legacy-SSE encoding, but lists its exceptions as "Type 4 Class" - the "Type 4 Class Exception Conditions" contains a list of Legacy-SSE instructions that are exempt from SSE's 16-byte alignment requirement, but MASKMOVDQU is missing from that list--> || {{yes|{{resize|85%|<code>VMASKMOVDQU</code>}}<br>(L{{=}}0){{efn|For AVX, masked stores to memory are also available using the <code>VMASKMOVPS</code> instruction with opcode {{nowrap|<code>VEX.66.0F38 2E /r</code>}} - unlike <code>VMASKMOVDQU</code>, this instruction allows 256-bit stores without temporal hints, although its mask is coarser - 4 bytes vs 1 byte per lane.}}}} || {{no|No{{efn|Opcode not available under AVX-512. Under AVX-512, unaligned masked stores to memory (albeit without temporal hints) can be done with the <code>VMOVDQU(8{{!}}16{{!}}32{{!}}64)</code> instructions with opcode {{nowrap|<code>EVEX.F2/F3.0F 7F /r</code>,}} using an opmask register to provide a write mask.}}}} ||{{n/a}}||{{n/a}}||{{n/a}} 
|-
! colspan=11 | Added with SSE2
|-
| colspan=2 | Multiply packed 32-bit unsigned integers, store full 64-bit result.<p>The input integers are taken from the low 32 bits of each 64-bit vector lane.</p> || <code>(V)PMULUDQ mm,mm/m64</code> || <code>0F F4 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| colspan=2 | Add packed 64-bit integers || <code>(V)PADDQ mm, mm/m64</code> || <code>0F D4 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64<!-- as of Feb 2024, listed in SDM rev 80 as one of the original MMX instructions, but this contradicts other sources of information, which list it as an instruction introduced with SSE2.-->
|-
| colspan=2 | Subtract packed 64-bit integers || <code>(V)PSUBQ mm,mm/m64</code> || <code>0F FB /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
! colspan=11 | Added with SSSE3
|-
| colspan=2 | [[Permute instruction|Vector Byte Shuffle]] || <code>(V)PSHUFB mm,mm/m64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 00 /r</code> || {{yes}}||{{yes|Yes{{efn|For AVX2 and AVX-512 with vectors wider than 128 bits, the <code>VPSHUFB</code> instruction is restricted to byte-shuffle within each 128-bit lane. Instructions that can do shuffles across 128-bit lanes include e.g. AVX2's <code>VPERMD</code> (shuffle of 32-bit lanes across 256-bit YMM register) and AVX512_VBMI's <code>VPERMB</code> (full byte shuffle across 64-byte ZMM register).}}}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| rowspan=2 | Pairwise horizontal add of packed integers
| 16-bit || <code>(V)PHADDW mm,mm/mm64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 01 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| 32-bit || <code>(V)PHADDD mm,mm/mm64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 02 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Pairwise horizontal add of packed 16-bit signed integers, with saturation || <code>(V)PHADDSW mm,mm/mm64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 03 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Multiply packed 8-bit signed and unsigned integers, add results pairwise into 16-bit signed integers with saturation. First operand is treated as unsigned, second operand as signed. || <code>(V)PMADDUBSW mm,mm/m64</code> || <code>0F38 04 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=2 | Pairwise horizontal subtract of packed integers.<p>The higher-order integer of each pair is subtracted from the lower-order integer.</p>
| 16-bit || <code>(V)PHSUBW mm,mm/m64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 05 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| 32-bit || <code>(V)PHSUBD mm,mm/m64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 06 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Pairwise horizontal subtract of packed 16-bit signed integers, with saturation  || <code>(V)PHSUBSW mm,mm/m64</code>{{efn|name="mmx2_lane128"}} || <code>0F38 07 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| rowspan=3 | Modify packed integers in first source argument based on the sign of packed signed integers in second source argument. The per-lane operation performed is:<pre>
if( src2 < 0 ) dst ← -src1
else if( src2 == 0 ) dst ← 0
else dst ← src1</pre>
| 8-bit || <code>(V)PSIGNB mm,mm/m64</code> || <code>0F38 08 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| 16-bit || <code>(V)PSIGNW mm,mm/m64</code> || <code>0F38 09 /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| {{nowrap|32-bit}} || <code>(V)PSIGND mm,mm/m64</code> || <code>0F38 0A /r</code> || {{yes}}||{{yes}}||{{yes}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Multiply packed 16-bit signed integers, then perform rounding and scaling to produce a 16-bit signed integer result.<p>The calculation performed per 16-bit lane is:<br>{{code|dst ← (src1*src2 + (1<<14)) >> 15}}</p> || <code>(V)PMULHRSW mm,mm/m64</code> || <code>0F38 0B /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| rowspan=4 | Absolute value of packed signed integers
| 8-bit || <code>(V)PABSB mm,mm/m64</code> || <code>0F38 1C /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 16-bit || <code>(V)PABSW mm,mm/m64</code> || <code>0F38 1D /r</code> || {{yes}}||{{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 32-bit
| <code>(V)PABSD mm,mm/m64</code>
| rowspan=2 | <code>0F38 1E /r</code>
| rowspan=2 {{yes|<code>PABSD</code>}}
| rowspan=2 {{yes|<code>PABSD</code>}}
| rowspan=2 {{yes|<code>VPABSD</code>}}
| {{yes|<code>VPABSD</code>(W0)}} || F || 32 || 32
|-
| 64-bit
| {{nowrap|<code>VPABSQ xmm,xmm/m128</code>(AVX-512)}}
| {{yes|<code>VPABSQ</code>(W1)}} || F || 64 || 64
|-
| colspan=2 | Packed Align Right.<p>Concatenate two input vectors into a double-size vector, then right-shift by the number of bytes specified by the imm8 argument. The shift-amount is not masked - if the shift-amount is greater than the input vector size, zeroes will be shifted in.</p>
| <code>(V)PALIGNR mm,mm/mm64,imm8</code>{{efn|name="mmx2_lane128"}} || {{nowrap|<code>0F3A 0F /r ib</code>}} || {{yes}}||{{yes}}||{{yes}}||{{yes|Yes{{efn|For AVX-512, <code>VPALIGNR</code> is supported but will perform its operation within each 128-bit lane. For packed alignment shifts that can shift data across 128-bit lanes, AVX512F's <code>VALIGND</code> instruction may be used, although its shift-amount is specified in units of 32-bits rather than bytes.}}}}||BW||8||{{no}}
|}
{{notelist}}
{{vpad}}
<!--Instructions other than the above that can touch MMX registers: MOVQ2DQ, MOVDQ2Q, CVTPS2PI, CVTPD2PI, CVTPI2PS, CVTPI2PD, CVTTPS2PI, CVTTPD2PI-->

== SSE instructions and extended variants thereof ==

=== Regularly-encoded floating-point SSE/SSE2 instructions, and AVX/AVX-512 extended variants thereof ===

For the instructions in the below table, the following considerations apply unless otherwise noted:
* Packed instructions are available at all vector lengths (128-bit for SSE2, 128/256-bit for AVX, 128/256/512-bit for AVX-512)
* FP32 variants of instructions are introduced as part of SSE. FP64 variants of instructions are introduced as part of SSE2.
* The AVX-512 variants of the FP32 and FP64 instructions are introduced as part of the AVX512F subset.
* For AVX-512 variants of the instructions, opmasks and broadcasts are available with a width of 32 bits for FP32 operations and 64 bits for FP64 operations. (Broadcasts are available for vector operations only.)

From SSE2 onwards, some data movement/bitwise instructions exist in three forms: an integer form, an FP32 form and an FP64 form. Such instructions are functionally identical, however some processors with SSE2 will implement integer, FP32 and FP64 execution units as three different execution clusters, where forwarding of results from one cluster to another may come with performance penalties and where such penalties can be minimzed by choosing instruction forms appropriately. (For example, there exists three forms of vector bitwise XOR instructions under SSE2 - <code>PXOR</code>, <code>XORPS</code>, and <code>XORPD</code> - these are intended for use on integer, FP32, and FP64 data, respectively.)
{|class="wikitable"
! style="min-width: 15em" rowspan=3 | Instruction Description
! rowspan=3 | Basic opcode
| scope="col" style="width: 1px; border-spacing:0; padding:0px" rowspan=42 |
! colspan=7 | Single Precision (FP32)
| scope="col" style="width: 1px; border-spacing:0; padding:0px" rowspan=42 |
! colspan=7 | Double Precision (FP64)
| scope="col" style="width: 1px; border-spacing:0; padding:0px" rowspan=42 |
! rowspan=3 {{vert header|{{resize|85%|AVX-512: RC/SAE}}}}
|-
! colspan=3 | Packed (no prefix)
| scope="col" style="width: 1px; border-spacing:0; padding:0px" rowspan=41 |
! colspan=3 | Scalar (F3h prefix)
! colspan=3 | Packed (66h prefix)
| scope="col" style="width: 1px; border-spacing:0; padding:0px" rowspan=41 |
! colspan=3 | Scalar (F2h prefix)
|-
! SSE instruction !! {{resize|75%|AVX<br>(VEX)}} !! {{resize|65%|AVX-512<br>(EVEX)}}
! SSE instruction !! {{resize|75%|AVX}}<br>{{resize|75%|(VEX)}}<wbr>{{efn|name="sse1_vexl1"|text=The VEX-prefix-encoded variants of the scalar instructions listed in this table should be encoded with VEX.L{{=}}0. Setting VEX.L{{=}}1 for any of these instructions is allowed but will result in what the Intel SDM describes as "unpredictable behavior across different processor generations".<!-- in the SDM, this effect is listed for every one of the scalar instructions except <code>MOVSD</code>,<code>RCPSS</code> and <code>RSQRTSS</code>, for which the effect of VEX.W=1 is simply not mentioned--> This also applies to VEX-encoded variants of <code>V(U)COMISS</code> and <code>V(U)COMISD</code>. (This behavior does not apply to scalar instructions outside this table, such as e.g. <code>VMOVD</code>/<code>VMOVQ</code>, where VEX.L{{=}}1 results in an #UD exception.)}} !! {{resize|65%|AVX-512<br>(EVEX)}}
! SSE2 instruction !! {{resize|75%|AVX<br>(VEX)}} !! {{resize|65%|AVX-512<br>(EVEX)}}
! SSE2 instruction !! {{resize|75%|AVX}}<br>{{resize|75%|(VEX)}}<wbr>{{efn|name="sse1_vexl1"}} !! {{resize|65%|AVX-512<br>(EVEX)}}
|-
| Unaligned load from memory or vector register || <code>0F 10 /r</code>
| <code>MOVUPS x,x/m128</code> || {{yes}} || {{yes|Yes{{efn|name="movaups_bcst"|EVEX-encoded variants of <code>VMOVAPS</code>, <code>VMOVUPS</code>, <code>VMOVAPD</code> and <code>VMOVUPD</code> support opmasks but do not support broadcast.}}}}
| <code>MOVSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>MOVUPD x,x/m128</code> || {{yes}} || {{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{nowrap|<code>MOVSD x,x/m64</code>}}{{efn|name="sse2_string_alias"|The SSE2 <code>MOVSD</code> (MOVe Scalar Double-precision) and <code>CMPSD</code> (CoMPare Scalar Double-precision) instructions have the same names as the older i386 <code>MOVSD</code> (MOVe String Doubleword) and <code>CMPSD</code> (CoMPare String Doubleword) instructions, however their operations are completely unrelated.<p>At the assembly language level, they can be distinguished by their use of XMM register operands.</p>}} || {{yes}} || {{yes}}
| {{no}}
|-
| Unaligned store to memory or vector register || <code>0F 11 /r</code>
| <code>MOVUPS x/m128,x</code> || {{yes}}||{{yes|Yes{{efn|name="movaups_bcst"}}}}
| <code>MOVSS x/m32,x</code> || {{yes}}||{{yes}}
| <code>MOVUPD x/m128,x</code> || {{yes}}||{{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{nowrap|<code>MOVSD x/m64,x</code>}}{{efn|name="sse2_string_alias"}} || {{yes}}||{{yes}}
| {{no}}
|-
| rowspan=2 | Load 64 bits from memory or upper half of XMM register into the lower half of XMM register while keeping the upper half unchanged
| rowspan=2 | <code>0F 12 /r</code>
| <code>MOVHLPS x,x</code> || {{yes|{{nowrap|(L0){{efn|name="sse1_vec128"|For variants of <code>VMOVLPS</code>, <code>VMOVHPS</code>, <code>VMOVLPD</code>, <code>VMOVHPD</code>, <code>VMOVLHPS</code>, <code>VMOVHLPS</code> encoded with VEX or EVEX prefixes, the only supported vector length is 128 bits (VEX.L{{=}}0 or EVEX.L{{=}}0).<p>For the EVEX-encoded variants, broadcasts and opmasks are not supported.</p>}}}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
| rowspan=2 {{n/a|(MOVSLDUP){{efn|name="sse1_noscalar"|The <code>MOVSLDUP</code>, <code>MOVSHDUP</code> and <code>MOVDDUP</code> instructions are not regularly-encoded scalar SSE1/2 instructions, but instead irregularly-assigned SSE3 vector instructions. For a description of these instructions, see table below.}}}} || rowspan=2 {{n/a|}} || rowspan=2 {{n/a|}}
| rowspan=2 | <code>MOVLPD x,m64</code> || rowspan=2 {{yes|{{nowrap|(L0){{efn|name="sse1_vec128"}}}}}} || rowspan=2 {{yes|(L0){{efn|name="sse1_vec128"}}}}
| rowspan=2 {{n/a|(MOVDDUP){{efn|name="sse1_noscalar"}}}} || rowspan=2 {{n/a|}} || rowspan=2 {{n/a|}}
| rowspan=2 {{no}}
|-
| <code>MOVLPS x,m64</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
|-
| Store 64 bits to memory from lower half of XMM register
| <code>0F 13 /r</code>
| <code>MOVLPS m64,x</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}} 
| {{no}}||{{no}}||{{no}}
| <code>MOVLPD m64,x</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Unpack and interleave low-order floating-point values
| <code>0F 14 /r</code>
| {{nowrap|<code>UNPCKLPS x,x/m128</code>}}
| {{yes|Yes{{efn|name="sse1_lane128"|For the <code>VUNPCK*</code>, <code>VSHUFPS</code> and <code>VSHUFPD</code> instructions, encodings with a vector-length wider than 128 bits are available under AVX2 and AVX-512, but the operation of such encodings is split into 128-bit lanes where each 128-bit lane internally performs the same operation as the 128-bit variant of the instruction (except that for <code>VSHUFPD</code>, each 128-bit lane will use a different 2-bit part of the instruction's imm8 argument).}}}}
| {{yes|Yes{{efn|name="sse1_lane128"}}}}
| {{no}}||{{no}}||{{no}}
| {{nowrap|<code>UNPCKLPD x,x/m128</code>}}||{{yes|Yes{{efn|name="sse1_lane128"}}}}||{{yes|Yes{{efn|name="sse1_lane128"}}}} 
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Unpack and interleave high-order floating-point values || <code>0F 15 /r</code>
| {{nowrap|<code>UNPCKHPS x,x/m128</code>}} || {{yes|Yes{{efn|name="sse1_lane128"}}}} || {{yes|Yes{{efn|name="sse1_lane128"}}}}
| {{no}}||{{no}}||{{no}}
| {{nowrap|<code>UNPCKHPD x,x/m128</code>}} || {{yes|Yes{{efn|name="sse1_lane128"}}}} || {{yes|Yes{{efn|name="sse1_lane128"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| rowspan=2 | Load 64 bits from memory or lower half of XMM register into the upper half of XMM register while keeping the lower half unchanged
| rowspan=2 | <code>0F 16 /r</code>
| <code>MOVLHPS x,x</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
| rowspan=2 {{n/a|(MOVSHDUP){{efn|name="sse1_noscalar"}}}} || rowspan=2 {{n/a|}} || rowspan=2 {{n/a|}}
| rowspan=2 | <code>MOVHPD x,m64</code> || rowspan=2 {{yes|(L0){{efn|name="sse1_vec128"}}}} || rowspan=2 {{yes|(L0){{efn|name="sse1_vec128"}}}}
| rowspan=2 {{no}} || rowspan=2 {{no}} || rowspan=2 {{no}}
| rowspan=2 {{no}}
|-
| <code>MOVHPS x,m64</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
|-
| Store 64 bits to memory from upper half of XMM register
| <code>0F 17 /r</code>
| <code>MOVHPS m64,x</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
| {{no}}||{{no}}||{{no}}
| <code>MOVHPD m64,x</code> || {{yes|(L0){{efn|name="sse1_vec128"}}}} || {{yes|(L0){{efn|name="sse1_vec128"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
! colspan=2 | || colspan=3 | || colspan=3 | || colspan=3 | || colspan=3 | 
|-
| Aligned load from memory or vector register 
| {{nowrap|<code>0F 28 /r</code>}}
| <code>MOVAPS x,x/m128</code> || {{yes}} || {{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| <code>MOVAPD x,x/m128</code> || {{yes}}||{{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Aligned store to memory or vector register
| <code>0F 29 /r</code>
| <code>MOVAPS x/m128,x</code> || {{yes}}||{{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| <code>MOVAPD x/m128,x</code> || {{yes}}||{{yes|Yes{{efn|name="movaups_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Integer to floating-point conversion using general-registers, MMX-registers or memory as source || <code>0F 2A /r</code>
| {{nowrap|{{resize|85%|<code>CVTPI2PS x,mm/m64</code>}}}}{{efn|name="sse1_cvtpi"|The <code>CVTPI2PS</code> and <code>CVTPI2PD</code> instructions take their input data as a vector of two 32-bit signed integers from either memory or MMX register. They will cause an x87→MMX transition even if the source operand is a memory operand.<p>For vector int→FP conversions that can accept an xmm/ymm/zmm register or vectors wider than 64 bits as input arguments, SSE2 provides the following irregularly-assigned instructions (see table below):<ul><li><code>CVTDQ2PS</code> (<code>0F 5B /r</code>)<li><code>CVTDQ2PD</code> (<code>F3 0F E6 /r</code>)</ul>These exist in AVX/AVX-512 extended forms as well.}} || {{no}} || {{no}}
| {{resize|85%|<code>CVTSI2SS x,r/m32</code><br/>{{nowrap|<code>CVTSI2SS x,r/m64</code>}}<br/>{{efn|name="sse_cvtsi2_64"|For the <code>(V)CVTSI2SS</code> and <code>(V)CVTSI2SD</code> instructions, variants with a 64-bit source argument are only available in 64-bit long mode and require REX.W, VEX.W or EVEX.W to be set to 1.<p>In 32-bit mode, their source argument is always 32-bit even if VEX.W or EVEX.W is set to 1.</p>}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{nowrap|{{resize|85%|<code>CVTPI2PD x,mm/m64</code>}}}}{{efn|name="sse1_cvtpi"}} || {{no}} || {{no}}
| {{resize|85%|<code>CVTSI2SD x,r/m32</code><br/>{{nowrap|<code>CVTSI2SD x,r/m64</code>}}<br>{{efn|name="sse_cvtsi2_64"}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| RC
|-
| Non-temporal store to memory from vector register.<p>The packed variants require aligned memory addresses even in VEX/EVEX-encoded forms.</p> || <code>0F 2B /r</code>
| <code>MOVNTPS m128,x</code> || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"|EVEX-encoded variants of<ul><li><code>VMOVNTPS</code>, <code>VMOVNTSS</code><li><code>VCOMISS</code>, <code>VCOMISD</code>, <code>VUCOMISS</code>, <code>VUCOMISD</code><li><code>VCVTSI2SS</code>, <code>VCTSI2SD</code><li><code>VCVT(T)SS2SI</code>,<code>VCVT(T)SD2SI</code></ul> support neither opmasks nor broadcast.}}}}
| {{maybe|<code>MOVNTSS m32,x</code><br>(AMD SSE4a)}} || {{no}}||{{no}}
| <code>MOVNTPD m128,x</code> || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{maybe|<code>MOVNTSD m64,x</code><br>(AMD SSE4a)}} || {{no}}||{{no}}
| {{no}}
|-
| Floating-point to integer conversion with truncation, using general-purpose registers or MMX-registers as destination
| <code>0F 2C /r</code>
| {{nowrap|{{resize|85%|<code>CVTTPS2PI mm,x/m64</code>}}}}<wbr>{{efn|name="sse1_cvt2pi"|The <code>CVT(T)PS2PI</code> and <code>CVT(T)PD2PI</code> instructions write their result to MMX register as a vector of two 32-bit signed integers.<p>For vector FP→int conversions that can write results to xmm/ymm/zmm registers, SSE2 provides the following irregularly-assigned instructions (see table below):<ul><li><code>CVTPS2DQ</code> (<code>66 0F 5B /r</code>)<li><code>CVTTPS2DQ</code> (<code>F3 0F 5B /r</code>)<li><code>CVTPD2DQ</code> (<code>F2 0F E6 /r</code>)<li><code>CVTTPD2DQ</code> (<code>66 0F E6 /r</code>)</ul>These exist in AVX/AVX-512 extended forms as well.}}  || {{no}} || {{no}}
| {{resize|80%|{{nowrap|<code>CVTTSS2SI r32,x/m32</code>}}<br/>{{nowrap|<code>CVTTSS2SI r64,x/m32</code>}}<wbr>{{efn|name="sse_cvt2si_64"|For the <code>(V)CVT(T)SS2SI</code> and <code>(V)CVT(T)SD2SI</code> instructions, variants with a 64-bit destination register are only available in 64-bit long mode and require REX.W, VEX.W or EVEX.W to be set to 1.<p>In 32-bit mode, their destination register is always 32-bit even if VEX.W or EVEX.W is set to 1.</p>}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{nowrap|{{resize|85%|<code>CVTTPD2PI mm,x/m64</code>}}}}<wbr>{{efn|name="sse1_cvt2pi"}} || {{no}} || {{no}}
| {{resize|80%|{{nowrap|<code>CVTTSD2SI r32,x/m64</code>}}<br/>{{nowrap|<code>CVTTSD2SI r64,x/m64</code>}}<wbr>{{efn|name="sse_cvt2si_64"}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| SAE
|-
| Floating-point to integer conversion, using general-purpose registers or MMX-registers as destination
| <code>0F 2D /r</code>
| {{nowrap|{{resize|85%|<code>CVTPS2PI mm,x/m64</code>}}}}{{efn|name="sse1_cvt2pi"}} || {{no}} || {{no}}
| {{resize|85%|{{nowrap|<code>CVTSS2SI r32,x/m32</code>}}<br/>{{nowrap|<code>CVTSS2SI r64,x/m32</code>}}<wbr>{{efn|name="sse_cvt2si_64"}}}} ||{{yes}}||{{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{nowrap|{{resize|85%|<code>CVTPD2PI mm,x/m64</code>}}}}{{efn|name="sse1_cvt2pi"}} || {{no}} || {{no}}
| {{resize|85%|{{nowrap|<code>CVTSD2SI r32,x/m64</code>}}<br/>{{nowrap|<code>CVTSD2SI r64,x/m64</code>}}<wbr>{{efn|name="sse_cvt2si_64"}}}} ||{{yes}}||{{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| RC
|-
| Unordered compare floating-point values and set EFLAGS.<p>Compares the bottom lanes of xmm vector registers.</p>
| <code>0F 2E /r</code>
| <code>UCOMISS x,x/m32</code> || {{yes|Yes{{efn|name="sse1_vexl1"}}}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| <code>UCOMISD x,x/m64</code> || {{yes|Yes{{efn|name="sse1_vexl1"}}}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| SAE
|-
| Compare floating-point values and set EFLAGS.<p>Compares the bottom lanes of xmm vector registers.</p>
| <code>0F 2F /r</code>
| <code>COMISS x,x/m32</code> || {{yes|Yes{{efn|name="sse1_vexl1"}}}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| <code>COMISD x,x/m64</code> || {{yes|Yes{{efn|name="sse1_vexl1"}}}} || {{yes|Yes{{efn|name="sse2_no_opmask_bcst"}}}}
| {{no}}||{{no}}||{{no}}
| SAE
|-
! colspan=2 | || colspan=3 | || colspan=3 | || colspan=3 | || colspan=3 |
|-
| Extract packed floating-point sign mask
| <code>0F 50 /r</code>
| {{nowrap|<code>MOVMSKPS r32,x</code>}} || {{yes}} || {{no|No{{efn|name="avx512_movmsk"|This instruction cannot be EVEX-encoded. Under AVX512DQ, extracting packed floating-point sign-bits can instead be done with the <code>VPMOVD2M</code> and <code>VPMOVQ2M</code> instructions.}}}}
| {{no}}||{{no}}||{{no}}
| {{nowrap|<code>MOVMSKPD r32,x</code>}} || {{yes}} || {{no|No{{efn|name="avx512_movmsk"}}}}
| {{no}}||{{no}}||{{no}}
| {{n/a}}
|-
| Floating-point Square Root
| <code>0F 51 /r</code>
| <code>SQRTPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>SQRTSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>SQRTPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>SQRTSD x,x/m64</code> || {{yes}} || {{yes}}
| RC
|-
| Reciprocal Square Root Approximation{{efn|name="sse1_rsqrterr"|The <code>(V)RCPSS</code>, <code>(V)RCPPS</code>, <code>(V)RSQRTSS</code> and <code>(V)RSQRTPS</code> approximation instructions compute their result with a relative error of at most <math>\pm 1.5*2^{-12}</math>. The exact calculation is implementation-specific and known to vary between different x86 CPUs.}}
| <code>0F 52 /r</code>
| {{nowrap|<code>RSQRTPS x,x/m128</code>}} || {{yes}} || {{no|No{{efn|name="sse1_a512_rsqrt"|This instruction cannot be EVEX-encoded. Instead, AVX512F provides different opcodes - {{nowrap|<code>EVEX.66.0F38 4E/4F /r</code>}} - for its new <code>VRSQRT14*</code> reciprocal square root approximation instructions.<p>The main difference between the AVX-512 <code>VRSQRT14*</code> instructions and the older SSE/AVX <code>(V)RSQRT*</code> instructions is that the AVX-512 <code>VRSQRT14*</code> instructions have their operation defined in a bit-exact manner, with a C reference model provided by Intel.<ref name="avx512_recip">Intel, [https://www.intel.com/content/www/us/en/developer/articles/code-sample/reference-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.html Reference Implementations for Intel Architecture Approximation Instructions VRCP14, VRSQRT14, VRCP28, VRSQRT28, and VEXP2], id #671685, Dec 28, 2015. [https://archive.today/20230918212656/https://www.intel.com/content/www/us/en/developer/articles/code-sample/reference-implementations-for-ia-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.html Archived] on Sep 18, 2023.<p>C code [https://www.intel.com/content/dam/develop/external/us/en/documents/recip14.c "recip14.c"] [https://web.archive.org/web/20230918213757/https://www.intel.com/content/dam/develop/external/us/en/documents/recip14.c archived] on 18 Sep 2023.</p></ref></p>}}}}
| {{nowrap|<code>RSQRTSS x,x/m32</code>}} || {{yes}} ||{{no|No{{efn|name="sse1_a512_rsqrt"}}}}
| {{no}} || {{no}} || {{no|No{{efn|name="sse1_a512_rsqrt"}}}}
| {{no}} || {{no}} || {{no|No{{efn|name="sse1_a512_rsqrt"}}}}
| {{n/a}}
|-
| Reciprocal Approximation{{efn|name="sse1_rsqrterr"}}
| <code>0F 53 /r</code>
| <code>RCPPS x,x/m128</code> || {{yes}} || {{no|No{{efn|name="sse1_a512_rcp"|This instruction cannot be EVEX-encoded. Instead, AVX512F provides different opcodes - {{nowrap|<code>EVEX.66.0F38 4C/4D /r</code>}} - for its new <code>VRCP14*</code> reciprocal approximation instructions.<p>The main difference between the AVX-512 <code>VRCP14*</code> instructions and the older SSE/AVX <code>(V)RCP*</code> instructions is that the AVX-512 <code>VRRCP14*</code> instructions have their operation defined in a bit-exact manner, with a C reference model provided by Intel.<ref name="avx512_recip" /></p>}}}}
| <code>RCPSS x,x/m32</code> || {{yes}} || {{no|No{{efn|name="sse1_a512_rcp"}}}}
| {{no}} || {{no}} || {{no|No{{efn|name="sse1_a512_rcp"}}}}
| {{no}} || {{no}} || {{no|No{{efn|name="sse1_a512_rcp"}}}}
| {{n/a}}
|-
| Vector bitwise AND
| <code>0F 54 /r</code>
| <code>ANDPS x,x/m128</code> || {{yes}} || {{yes|{{nowrap|(DQ){{efn|name="sse1_bitop"|The EVEX-encoded versions of the <code>VANDPS</code>, <code>VANDPD</code>, <code>VANDNPS</code>, <code>VANDNPD</code>, <code>VORPS</code>, <code>VORPD</code>, <code>VXORPS</code>, <code>VXORPD</code> instructions are not introduced as part of the AVX512F subset, but instead the AVX512DQ subset.}}}}}}
| {{no}}||{{no}}||{{no}}
| <code>ANDPD x,x/m128</code> || {{yes}} || {{yes|{{nowrap|(DQ){{efn|name="sse1_bitop"}}}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Vector bitwise AND-NOT
| <code>0F 55 /r</code>
| <code>ANDNPS x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| <code>ANDNPD x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Vector bitwise OR
| <code>0F 56 /r</code>
| <code>ORPS x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| <code>ORPD x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
| Vector bitwise XOR{{efn|<code>XORPS</code>/<code>VXORPS</code> with both source operands being the same register is commonly used as a register-zeroing idiom, and is recognized by most x86 CPUs as an instruction that does not depend on its source arguments.<br/>Under AVX or AVX-512, it is recommended to use a 128-bit form of <code>VXORPS</code> for this purpose - this will, on some CPUs, result in fewer micro-ops than wider forms while still achieving register-zeroing of the whole 256 or 512 bit vector-register.}}
| <code>0F 57 /r</code>
| <code>XORPS x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| <code>XORPD x,x/m128</code> || {{yes}} || {{yes|(DQ){{efn|name="sse1_bitop"}}}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|-
! colspan=2 | || colspan=3 | || colspan=3 | || colspan=3 | || colspan=3 | 
|-
| Floating-point Add
| <code>0F 58 /r</code>
| <code>ADDPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>ADDSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>ADDPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>ADDSD x,x/m64</code> || {{yes}} || {{yes}}
| RC
|-
| Floating-point Multiply
| <code>0F 59 /r</code>
| <code>MULPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>MULSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>MULPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>MULSD x,x/m64</code> || {{yes}} || {{yes}}
| RC
|-
| Convert between floating-point formats<br/>(FP32→FP64, FP64→FP32)
| <code>0F 5A /r</code>
| {{nowrap|<code>CVTPS2PD x,x/m64</code>}}<br/>(SSE2) || {{yes}} || {{yes|Yes{{efn|name="sse2_fpfp_opmask"|For EVEX-encoded variants of conversions between FP formats of different widths, the opmask lane width is determined by the result format: 64-bit for <code>VCVTPS2PD</code> and <code>VCVTSS2SD</code> and 32-bit for <code>VCVTPD2PS</code> and <code>VCVTSS2SD</code>.}}}}
| {{nowrap|{{resize|85%|<code>CVTSS2SD x,x/m32</code>}}}}<br/>(SSE2) || {{yes}} || {{yes|Yes{{efn|name="sse2_fpfp_opmask"}}}}
| {{nowrap|{{resize|85%|<code>CVTPD2PS x,x/m128</code>}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_fpfp_opmask"}}}}
| {{nowrap|{{resize|85%|<code>CVTSD2SS x,x/m64</code>}}}} || {{yes}} || {{yes|Yes{{efn|name="sse2_fpfp_opmask"}}}}
| SAE,<br>RC{{efn|Widening FP→FP conversions (<code>CVTPS2PD</code>, <code>CVTSS2SD</code>, <code>VCVTPH2PD</code>, <code>VCVTSH2SD</code>) support the SAE modifier. Narrowing conversions (<code>CVTPD2PS</code>, <code>CVTSD2SS</code>) support the RC modifier.}}
|-
| Floating-point Subtract
| <code>0F 5C /r</code>
| <code>SUBPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>SUBSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>SUBPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>SUBSD x,x/m64</code> || {{yes}} || {{yes}}
| RC
|-
| Floating-point Minimum Value{{efn|name="sse1_minmax"|For the floating-point minimum-value and maximum-value instructions <code>(V)MIN*</code> and <code>(V)MAX*</code>, if the two input operands are both zero or at least one of the input operands is NaN, then the second input operand is returned. This matches the behavior of common C programming-language expressions such as {{nowrap|<code>((op1)&gt;(op2)?(op1):(op2))</code>}} for maximum-value and {{nowrap|<code>((op1)&lt;(op2)?(op1):(op2))</code>}} for minimum-value.}}
| <code>0F 5D /r</code>
| <code>MINPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>MINSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>MINPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>MINSD x,x/m64</code> || {{yes}} || {{yes}}
| SAE
|-
| Floating-point Divide
| <code>0F 5E /r</code>
| <code>DIVPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>DIVSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>DIVPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>DIVSD x,x/m64</code> || {{yes}} || {{yes}}
| RC
|-
| Floating-point Maximum Value{{efn|name="sse1_minmax"}}
| <code>0F 5F /r</code>
| <code>MAXPS x,x/m128</code> || {{yes}} || {{yes}}
| <code>MAXSS x,x/m32</code> || {{yes}} || {{yes}}
| <code>MAXPD x,x/m128</code> || {{yes}} || {{yes}}
| <code>MAXSD x,x/m64</code> || {{yes}} || {{yes}}
| SAE
|-
! colspan=2 | || colspan=3 | || colspan=3 | || colspan=3 | || colspan=3 | 
|-
| Floating-point compare. Result is written as all-0s/all-1s values (all-1s for comparison true) to vector registers for SSE/AVX, but opmask register for AVX-512. Comparison function is specified by imm8 argument.{{efn|text=For the SIMD floating-point compares, the imm8 argument has the following format:
{{{!}} class="wikitable"
! Bits !! Usage
{{!}}-
{{!}} 1:0 {{!!}} Basic comparison predicate
{{!}}-
{{!}} 2 {{!!}} Invert comparison result
{{!}}-
{{!}} 3 {{!!}} Invert comparison result if unordered (VEX/EVEX only)
{{!}}-
{{!}} 4 {{!!}} Invert signalling behavior (VEX/EVEX only)
{{!}}}
The basic comparison predicates are:
{{{!}} class="wikitable"
! Value !! Meaning
{{!}}-
{{!}} 00b {{!!}} Equal (non-signalling)
{{!}}-
{{!}} 01b {{!!}} Less-than (signalling)
{{!}}-
{{!}} 10b {{!!}} Less-than-or-equal (signalling)
{{!}}-
{{!}} 11b {{!!}} Unordered (non-signalling)
{{!}}}
A signalling compare will cause an exception if any of the inputs are QNaN.
}}
| {{nowrap|{{resize|85%|<code>0F C2 /r ib</code>}}}}
| {{nowrap|{{resize|85%|<code>CMPPS x,x/m128,imm8</code>}}}} || {{yes}} || {{yes}}
| {{nowrap|{{resize|85%|<code>CMPSS x,x/m32,imm8</code>}}}} || {{yes}} || {{yes}}
| {{nowrap|{{resize|85%|<code>CMPPD x,x/m128,imm8</code>}}}} || {{yes}} || {{yes}}
| {{nowrap|{{resize|85%|<code>CMPSD x,x/m64,imm8</code>}}}}<br/>{{efn|name="sse2_string_alias"}} || {{yes}} || {{yes}}
| SAE
|-
| Packed Interleaved Shuffle.<p>Performs a shuffle on each of its two input arguments, then keeps the bottom half of the shuffle result from its first argument and the top half of the shuffle result from its second argument.</p>
| {{nowrap|{{resize|85%|<code>0F C6 /r ib</code>}}}}
| {{nowrap|{{resize|80%|<code>SHUFPS x,x/m128,imm8</code>}}}}<wbr>{{efn|name="sse1_lane128"}} || {{yes}} || {{yes}}
| {{no}}||{{no}}||{{no}}
| {{nowrap|{{resize|80%|<code>SHUFPD x,x/m128,imm8</code>}}}}<wbr>{{efn|name="sse1_lane128"}} || {{yes}} || {{yes}}
| {{no}}||{{no}}||{{no}}
| {{no}}
|}
{{notelist}}
{{vpad}}

=== Integer SSE2/4 instructions with 66h prefix, and AVX/AVX-512 extended variants thereof ===

These instructions do not have any MMX forms, and do not support any encodings without a prefix.
Most of these instructions have extended variants available in VEX-encoded and EVEX-encoded forms:
* The VEX-encoded forms are available under AVX/AVX2. Under AVX, they are available only with a vector length of 128 bits (VEX.L=0 enocding) - under AVX2, they are (with some exceptions noted with "L=0") also made available with a vector length of 256 bits.
* The EVEX-encoded forms are available under AVX-512 - the specific AVX-512 subset needed for each instruction is listed along with the instruction.

{| class="wikitable"
! rowspan=2 colspan=2 | Description
! rowspan=2 | Instruction mnemonics
! rowspan=2 | Basic opcode
! rowspan=2 | SSE (66h prefix)
! rowspan=2 | AVX<br>(VEX.66 prefix)
! colspan=4 | AVX-512 (EVEX.66 prefix)
|-
! supported !! subset !! lane !! bcst
|-
! colspan=10 | Added with SSE2
|-
| colspan=2 | Unpack and interleave low-order 64-bit integers|| <code>(V)PUNPCKLQDQ xmm,xmm/m128</code>{{efn|name="isse_lane128"}} || <code>0F 6C /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| colspan=2 | Unpack and interleave high-order 64-bit integers|| <code>(V)PUNPCKHQDQ xmm,xmm/m128</code>{{efn|name="isse_lane128"}} || <code>0F 6D /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| colspan=2 | Right-shift 128-bit unsigned integer by specified number of bytes || <code>(V)PSRLDQ xmm,imm8</code>{{efn|name="isse_lane128"}} || {{nowrap|<code>0F 73 /3 ib</code>}} ||{{yes}}||{{yes}}||{{yes}}||BW||{{no}}||{{no}}
|-
| colspan=2 | Left-shift 128-bit integer by specified number of bytes || <code>(V)PSLLDQ xmm,imm8</code>{{efn|name="isse_lane128"}} || <code>0F 73 /7 ib</code> ||{{yes}}||{{yes}}||{{yes}}||BW||{{no}}||{{no}}
|-
| colspan=2 | Move 64-bit scalar value from xmm register to xmm register or memory || <code>(V)MOVQ xmm/m64,xmm</code> || <code>0F D6 /r</code> || {{yes}}||{{yes|Yes (L{{=}}0)}}||{{yes|Yes <br/>(L{{=}}0,W{{=}}1)}}||F||{{no}}||{{no}}
|-
! colspan=10 | Added with SSE4.1
|-
| colspan=2 | Variable blend packed bytes.<p>For each byte lane of the result, pick the value from either the first or the second argument depending on the top bit of the corresponding byte lane of <code>XMM0</code>.</p> || <code>PBLENDVB xmm,xmm/m128</code><br/>{{nowrap|<code>PBLENDVB xmm,xmm/m128,XMM0</code>{{efn|Assemblers may accept <code>PBLENDVB</code> with or without <code>XMM0</code> as a third argument.}}}} || <code>0F38 10 /r</code> ||{{yes}}||{{no|No{{efn|name="isse_vpblendvb"|The <code>PBLENDVB</code> instruction with opcode {{nowrap|<code>66 0F38 10 /r</code>}} is not VEX-encodable. AVX does provide a <code>VPBLENDVB</code> instruction that is similar to <code>PBLENDVB</code>, however, it uses a different opcode and operand encoding - {{nowrap|<code>VEX.66.0F3A.W0 4C /r /is4</code>.}}}}}}||{{no|No{{efn|Opcode not EVEX-encodable. Under AVX-512, variable blend of packed bytes may be done with the <code>VPBLENDMB</code> instruction (opcode <code>EVEX.66.0F38.W0 66 /r</code>).}}}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| rowspan=6 | Sign-extend packed integers into wider packed integers
| 8-bit → 16-bit || <code>(V)PMOVSXBW xmm,xmm/m64</code> || <code>0F38 20 /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 8-bit → 32-bit || <code>(V)PMOVSXBD xmm,xmm/m32</code> || <code>0F38 21 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||32||{{no}}
|-
| 8-bit → 64-bit || <code>(V)PMOVSXBQ xmm,xmm/m16</code> || <code>0F38 22 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||64||{{no}}
|-
| 16-bit → 32-bit || <code>(V)PMOVSXWD xmm,xmm/m64</code> || <code>0F38 23 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||32||{{no}}
|-
| 16-bit → 64-bit || <code>(V)PMOVSXWQ xmm,xmm/m32</code> || <code>0F38 24 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||64||{{no}}
|-
| 32-bit → 64-bit || <code>(V)PMOVSXDQ xmm,xmm/m64</code> || <code>0F38 25 /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||64||{{no}}
|-
! colspan=10 |
|-
| colspan=2 | Multiply packed 32-bit signed integers, store full 64-bit result.<p>The input integers are taken from the low 32 bits of each 64-bit vector lane.</p> || <code>(V)PMULDQ xmm,xmm/m128</code> || <code>0F38 28 /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}1)}}||F||64||64
|-
| colspan=2 | Compare packed 64-bit integers for equality || <code>(V)PCMPEQQ xmm,xmm/m128</code> || <code>0F38 29 /r</code> ||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1){{efn|name="pcmp512b"|The EVEX-encoded variants of the <code>VPCMPEQ*</code> and <code>VPCMPGT*</code> instructions write their results to AVX-512 opmask registers. This differs from the older non-EVEX variants, which write comparison results as vectors of all-0s/all-1s values to the regular mm/xmm/ymm vector registers.}}}}||F||64||64
|-
| colspan=2 | Aligned non-temporal vector load from memory.{{efn|The load performed by <code>(V)MOVNTDQA</code> is weakly-ordered. It may be reordered with respect to other loads, stores and even <code>LOCK</code>s - to impose ordering with respect to other loads/stores, <code>MFENCE</code> or serialization is needed.<p>If <code>(V)MOVNTDQA</code> is used with uncached memory, it may fetch a cache-line-sized block of data around the data actually requested - subsequent <code>(V)MOVNTDQA</code> instructions may return data from blocks fetched in this manner as long as they are not separated by an <code>MFENCE</code> or serialization.</p>}} || <code>(V)MOVNTDQA xmm,m128</code> || <code>0F38 2A /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||{{no}}||{{no}}
|-
| colspan=2 | Pack 32-bit unsigned integers to 16-bit, with saturation || {{nowrap|<code>(V)PACKUSDW xmm, xmm/m128</code>{{efn|name="isse_lane128"|For the <code>(V)PUNPCK*</code>, <code>(V)PACKUSDW</code>, <code>(V)PBLENDW</code>, <code>(V)PSLLDQ</code> and <code>(V)PSLRDQ</code> instructions, encodings with a vector-length wider than 128 bits are available under AVX2 and/or AVX-512, but the operation of such encodings is split into 128-bit lanes where each 128-bit lane internally performs the same operation as the 128-bit variant of the instruction.}}}} || <code>0F38 2B /r</code> ||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||BW||16||32
|-
! colspan=10 |
|-
| rowspan=6 | Zero-extend packed integers into wider packed integers
| 8-bit → 16-bit || <code>(V)PMOVZXBW xmm,xmm/m64</code> || <code>0F38 30 /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 8-bit → 32-bit || <code>(V)PMOVZXBD xmm,xmm/m32</code> || <code>0F38 31 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||32||{{no}}
|-
| 8-bit → 64-bit || <code>(V)PMOVZXBQ xmm,xmm/m16</code> || <code>0F38 32 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||64||{{no}}
|-
| 16-bit → 32-bit || <code>(V)PMOVZXWD xmm,xmm/m64</code> || <code>0F38 33 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||32||{{no}}
|-
| 16-bit → 64-bit || <code>(V)PMOVZXWQ xmm,xmm/m32</code> || <code>0F38 34 /r</code> || {{yes}}||{{yes}}||{{yes}}||F||64||{{no}}
|-
| {{nowrap|32-bit → 64-bit}} || <code>(V)PMOVZXDQ xmm,xmm/m64</code> || <code>0F38 35 /r</code> || {{yes}}||{{yes}}||{{yes|Yes (W{{=}}0)}}||F||64||{{no}}
|-
! colspan=10 |
|-
| rowspan=3 | Packed minimum-value of signed integers
| 8-bit || <code>(V)PMINSB xmm,xmm/m128</code> || <code>0F38 38 /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 32-bit
| <code>(V)PMINSD xmm,xmm/m128</code>
| rowspan=2 | <code>0F38 39 /r</code>
| rowspan=2 {{yes|<code>PMINSD</code>}}
| rowspan=2 {{yes|<code>VPMINSD</code>}}
| {{yes|<code>VPMINSD</code>(W0)}}||F||32||32
|-
| 64-bit
| <code>VPMINSQ xmm,xmm/m128</code>(AVX-512)
| {{yes|<code>VPMINSQ</code>(W1)}}||F||64||64
|-
| rowspan=3 | Packed minimum-value of unsigned integers

| 16-bit || <code>(V)PMINUW xmm,xmm/m128</code> || <code>0F38 3A /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 32-bit
| <code>(V)PMINUD xmm,xmm/m128</code><br>
| rowspan=2 | <code>0F38 3B /r</code>
| rowspan=2 {{yes|<code>PMINUD</code>}}
| rowspan=2 {{yes|<code>VPMINUD</code>}}
| {{yes|<code>VPMINUD</code>(W0)}}||F||32||32
|-
| 64-bit
| <code>VPMINUQ xmm,xmm/m128</code>(AVX-512)
| {{yes|<code>VPMINUQ</code>(W1)}}||F||64||64
|-
| rowspan=3 | Packed maximum-value of signed integers
| 8-bit || <code>(V)PMAXSB xmm,xmm/m128</code> || <code>0F38 3C /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||8||{{no}}
|-
| 32-bit
| <code>(V)PMAXSD xmm,xmm/m128</code>
| rowspan=2 | <code>0F38 3D /r</code>
| rowspan=2 {{yes|<code>PMAXSD</code>}}
| rowspan=2 {{yes|<code>VPMAXSD</code>}}
| {{yes|<code>VPMAXSD</code>(W0)}}||F||32||32
|-
| 64-bit
| <code>VPMAXSQ xmm,xmm/m128</code>(AVX-512)
| {{yes|<code>VPMAXSQ</code>(W1)}}||F||64||64
|-
| rowspan=3 | Packed maximum-value of unsigned integers
| 16-bit || <code>(V)PMAXUW xmm,xmm/m128</code> || <code>0F38 3E /r</code> || {{yes}}||{{yes}}||{{yes}}||BW||16||{{no}}
|-
| 32-bit
| <code>(V)PMAXUD xmm,xmm/m128</code><br>
| rowspan=2 | <code>0F38 3F /r</code>
| rowspan=2 {{yes|<code>PMAXUD</code>}}
| rowspan=2 {{yes|<code>VPMAXUD</code>}}
| {{yes|<code>VPMAXUD</code>(W0)}}||F||32||32
|-
| 64-bit
| <code>VPMAXUQ xmm,xmm/m128</code>(AVX-512)
| {{yes|<code>VPMAXUQ</code>(W1)}}||F||64||64
|-
! colspan=10 |
|-
| rowspan=2 colspan=2 | Multiply packed 32/64-bit integers, store low half of results
| rowspan=2 | <code>(V)PMULLD mm,mm/m64</code><br>{{nowrap|<code>PMULLQ xmm,xmm/m128</code>}}(AVX-512)
| rowspan=2 | <code>0F38 40 /r</code>
| rowspan=2 {{yes|<code>PMULLD</code>}}
| rowspan=2 {{yes|<code>VPMULLD</code>}}
| {{yes|<code>VPMULLD</code>(W0)}} || F || 32 || 32
|-
| {{yes|<code>VPMULLQ</code>(W1)}} || DQ || 64 || 64
|-
| colspan=2 | Packed Horizontal Word Minimum<p>Find the smallest 16-bit integer in a packed vector of 16-bit unsigned integers, then return the integer and its index in the bottom two 16-bit lanes of the result vector.</p> || {{nowrap|<code>(V)PHMINPOSUW xmm,xmm/m128</code>}} || <code>0F38 41 /r</code> || {{yes}}||{{yes|Yes (L{{=}}0)}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Blend Packed Words.<p>For each 16-bit lane of the result, pick a 16-bit value from either the first or the second source argument depending on the corresponding bit of the imm8.</p> || {{nowrap|<code>(V)PBLENDW xmm,xmm/m128,imm8</code>{{efn|name="isse_lane128"}}}} || {{nowrap|<code>0F3A 0E /r ib</code>}} || {{yes}}||{{yes|Yes{{efn|For AVX, the <code>VBLENDPS</code> and <code>VPBLENDD</code> instructions can be used to perform a blend with 32-bit lanes, allowing one imm8 mask to span a full 256-bit vector without repetition.}}}}||{{no|No{{efn|Opcode not EVEX-encodable. Under AVX-512, variable blend of packed words may be done with the <code>VPBLENDMW</code> instruction (opcode <code>EVEX.66.0F38.W1 66 /r</code>).}}}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
! colspan=10 |
|-
| rowspan=4 | Extract integer from indexed lane of vector register, and store to GPR or memory.<p>Zero-extended if stored to GPR.</p>
| 8-bit || {{nowrap|<code>(V)PEXTRB r32/m8,xmm,imm8</code>{{efn|name="isse_pextr"| For <code>(V)PEXTRB</code> and <code>(V)PEXTRW</code>, if the destination argument is a register, then the extracted 8/16-bit value is zero-extended to 32/64 bits.}}}}  || <code>0F3A 14 /r ib</code> || {{yes}}|| {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0)}} || BW || {{no}} || {{no}}
|-
| 16-bit || {{nowrap|<code>(V)PEXTRW r32/m16,xmm,imm8</code>{{efn|name="isse_pextr"}}}} || <code>0F3A 15 /r ib</code> || {{yes}}|| {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0)}} || BW || {{no}} || {{no}}
|-
| 32-bit 
| <code>(V)PEXTRD r/m32,xmm,imm8</code>
| rowspan=2 | <code>0F3A 16 /r ib</code> 
| {{yes}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}0)}}{{efn|name="vpextrd_vexw1"|1=For the <code>VPEXTRD</code> and <code>VPINSRD</code> instructions in non-64-bit mode, the instructions are documented as being permitted to be encoded with VEX.W=1 on Intel<ref>Intel, [https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Intel 64 and IA-32 Architectures Software Developer’s Manual] order no. 325462-086, December 2024, Volume 2B, <code>VPEXTRD</code> entry on page 1511 and <code>VPINSRD</code> entry on page 1530. [https://web.archive.org/web/20241230194917/https://cdrdv2-public.intel.com/843820/325462-sdm-vol-1-2abcd-3abcd-4-1.pdf Archived] on 30 Dec 2024.</ref> but not AMD<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf AMD64 Architecture Programmer’s Manual Volumes 1–5], pub.no. 40332, rev 4.08, April 2024, see entry for <code>VPEXTRD</code> on page 2302 and <code>VPINSRD</code> on page 2329. [https://web.archive.org/web/20250119235947/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/40332.pdf Archived] on 19 Jan 2025.</ref> CPUs (although exceptions to this do exist, e.g. [[Bulldozer (microarchitecture)|Bulldozer]] permits such encodings<ref>AMD, [https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/revision-guides/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf Revision Guide for AMD Family 15h Models 00h-0Fh Processors], pub.no. 38603 rev 3.24, sep 2014, see erratum 592 on page 37. [https://web.archive.org/web/20250122022115/https://www.amd.com/content/dam/amd/en/documents/archived-tech-docs/revision-guides/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf Archived] on 22 Jan 2025.</ref> while [[Sandy Bridge]] does not<ref>Intel, [https://web.archive.org/web/20170706071646/https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-desktop-specification-update.pdf 2nd Generation Intel Core Processor Family Desktop Specification Update], order no. 324643-037, apr 2016, see erratum BJ72 on page 43. Archived from the [https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/2nd-gen-core-desktop-specification-update.pdf original] on 6 Jul 2017.</ref>)<br/>In 64-bit mode, these instructions require VEX.W=0 on both Intel and AMD processors — encodings with VEX.W=1 are interpreted as <code>VPEXTRQ</code>/<code>VPINSRQ</code>.}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}0)}} || DQ || {{no}} || {{no}}
|-
| 64-bit<br/>(x86-64)
| {{nowrap|<code>(V)PEXTRQ r/m64,xmm,imm8</code>}}
| {{yes|Yes<br/>(REX.W)}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}1)}}
| {{yes|Yes<br>(L{{=}}0,W{{=}}1)}} || DQ || {{no}} || {{no}}
|-
| rowspan=3 | Insert integer from general-purpose register into indexed lane of vector register
| 8-bit || <code>(V)PINSRB xmm,r32/m8,imm8</code>{{efn|In the case of a register source argument to <code>(V)PINSRB</code>, the argument is considered to be a 32-bit register of which the 8 bottom bits are used, not an 8-bit register proper. This means that it is not possible to specify AH/BH/CH/DH as a source argument to <code>(V)PINSRB</code>.}} || <code>0F3A 20 /r ib</code> || {{yes}}|| {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0)}} || BW || {{no}} || {{no}}
|-
| 32-bit
| <code>(V)PINSRD xmm,r32/m32,imm8</code>
| rowspan=2 | <code>0F3A 22 /r ib</code>
| {{yes}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}0)}}{{efn|name="vpextrd_vexw1"}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}0)}} || DQ || {{no}} || {{no}}
|-
| 64-bit<br/>(x86-64)
| {{nowrap|<code>(V)PINSRQ xmm,r64/m64,imm8</code>}}
| {{yes|Yes<br/>(REX.W)}}
| {{yes|Yes<br/>(L{{=}}0,W{{=}}1)}}
| {{yes|Yes<br>(L{{=}}0,W{{=}}1)}} || DQ || {{no}} || {{no}}
|-
! colspan=10 |
|-
| colspan=2 | Compute Multiple Packed Sums of Absolute Difference.<p>The 128-bit form of this instruction computes 8 sums of absolute differences from sequentially selected groups of four bytes in the first source argument and a selected group of four contiguous bytes in the second source operand, and writes the sums to sequential 16-bit lanes of destination register. If the two source arguments <code>src1</code> and <code>src2</code> are considered to be two 16-entry arrays of uint8 values and <code>temp</code> is considered to be an 8-entry array of uint16 values, then the operation of the instruction is:</p><pre>for i = 0 to 7 do
    temp[i] := 0
    for j = 0 to 3 do
         a := src1[ i+(imm8[2]*4)+j ]
         b := src2[ (imm8[1:0]*4)+j ]
         temp[i] := temp[i] + abs(a-b)
    done
done
dst := temp</pre>
For wider forms of this instruction under AVX2 and AVX10.2, the operation is split into 128-bit lanes where each lane internally performs the same operation as the 128-bit variant of the instruction - except that odd-numbered lanes use bits 5:3 rather than bits 2:0 of the imm8.
|| {{nowrap|<code>(V)MPSADBW xmm,xmm/m128,imm8</code>}} || {{nowrap|<code>0F3A 42 /r ib</code>}} || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || 10.2{{efn|EVEX-encoded variants of the <code>VMPSADBW</code> instruction are only available if AVX10.2 is supported.}} || 16 || {{no}}
|-
! colspan=10 | Added with SSE 4.2
|-
| colspan=2 | Compare packed 64-bit signed integers for greater-than || <code>(V)PCMPGTQ xmm, xmm/m128</code> || <code>0F38 37 /r</code> ||{{yes}}||{{yes}}||{{yes|Yes (W{{=}}1){{efn|name="pcmp512b"}}}}||F||64||64
|-
| colspan=2 | Packed Compare Explicit Length Strings, Return Mask || {{nowrap|<code>(V)PCMPESTRM xmm,xmm/m128,imm8</code>}} || <code>0F3A 60 /r ib</code> || {{yes|Yes{{efn|name="isse_pcmpstr"|The SSE4.2 packed string compare <code>PCMP*STR*</code> instructions allow their 16-byte memory operands to be misaligned even when using legacy SSE encoding.}}}}||{{yes|Yes (L{{=}}0)}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Packed Compare Explicit Length Strings, Return Index || <code>(V)PCMPESTRI xmm,xmm/m128,imm8</code> || <code>0F3A 61 /r ib</code> || {{yes|Yes{{efn|name="isse_pcmpstr"}}}} ||{{yes|Yes (L{{=}}0)}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Packed Compare Implicit Length Strings, Return Mask || <code>(V)PCMPISTRM xmm,xmm/m128,imm8</code> || <code>0F3A 62 /r ib</code> || {{yes|Yes{{efn|name="isse_pcmpstr"}}}} ||{{yes|Yes (L{{=}}0)}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| colspan=2 | Packed Compare Implicit Length Strings, Return Index || <code>(V)PCMPISTRI xmm,xmm/m128,imm8</code> || <code>0F3A 63 /r ib</code> ||  {{yes|Yes{{efn|name="isse_pcmpstr"}}}} ||{{yes|Yes (L{{=}}0)}}||{{no}}||{{n/a}}||{{n/a}}||{{n/a}}
|}
{{notelist}}
{{vpad}}

=== Other SSE/2/3/4 SIMD instructions, and AVX/AVX-512 extended variants thereof ===

SSE SIMD instructions that do not fit into any of the preceding groups. Many of these instructions have AVX/AVX-512 extended forms - unless otherwise indicated (L=0 or footnotes) these extended forms support 128/256-bit operation under AVX and 128/256/512-bit operation under AVX-512.

{|class="wikitable"
! rowspan=2 colspan=2 | Description
! rowspan=2 | Instruction mnemonics
! rowspan=2 | Basic opcode
! rowspan=2 | &nbsp;&nbsp;SSE&nbsp;&nbsp;
! rowspan=2 | AVX<br>(VEX prefix)
! colspan=5 | AVX-512 (EVEX prefix)
|-
! supported !! subset !! lane !! bcst !! rc/sae
|-
! colspan=11 | Added with SSE
|-
| colspan=2 | Load MXCSR (Media eXtension Control and Status Register) from memory || <code>(V)LDMXCSR m32</code> || <code>NP 0F AE /2</code> || {{yes}} || {{yes|Yes<br/>(L{{=}}0)}} || {{no}} || {{n/a}}  || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | Store MXCSR to memory || <code>(V)STMXCSR m32</code> || <code>NP 0F AE /3</code> || {{yes}} || {{yes|Yes<br/>(L{{=}}0)}} || {{no}} || {{n/a}}  || {{n/a}} || {{n/a}} || {{n/a}}
|-
! colspan=11 | Added with SSE2
|-
| colspan=2 | Move a 64-bit data item from MMX register to bottom half of XMM register. Top half is zeroed out. || <code>MOVQ2DQ xmm,mm</code> || <code>F3 0F D6 /r</code> || {{yes}} || {{no}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | Move a 64-bit data item from bottom half of XMM register to MMX register.<!-- The intel SDM entry for MOVDQ2D does not mention which instruction set extension it comes from and uses a different description box format than most other instructions--> || <code>MOVDQ2Q mm,xmm</code> || <code>F2 0F D6 /r</code> || {{yes}} || {{no}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | Load a 64-bit integer from memory or XMM register to bottom 64 bits of XMM register, with zero-fill || <code>(V)MOVQ xmm,xmm/m64</code> || <code>F3 0F 7E /r</code> || {{yes}} || {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0,W{{=}}1)}} || F || {{no}} || {{no}} || {{no}}
|-
| rowspan=4 colspan=2 | Vector load from unaligned memory or vector register || rowspan=4 | <code>(V)MOVDQU xmm,xmm/m128</code> || rowspan=2 | <code>F3 0F 6F /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || {{yes|<code>VMOVDQU64</code>(W1)}} || F || 64 || {{no}} || {{no}}
|-
| {{yes|<code>VMOVDQU32</code>(W0)}} || F || 32 || {{no}} || {{no}}
|-
| rowspan=2 | <code>F2 0F 6F /r</code> || rowspan=2 {{no}} || rowspan=2 {{no}} || {{yes|<code>VMOVDQU16</code>(W1)}} || BW || 16 || {{no}} || {{no}}
|-
| {{yes|<code>VMOVDQU8</code>(W0)}} || BW || 8 || {{no}} || {{no}}
|-
| rowspan=4  colspan=2 | Vector store to unaligned memory or vector register || rowspan=4 | <code>(V)MOVDQU xmm/m128,xmm</code> || rowspan=2 | <code>F3 0F 7F /r</code> || rowspan=2 {{yes}} || rowspan=2 {{yes}} || {{yes|<code>VMOVDQU64</code>(W1)}} || F || 64 || {{no}} || {{no}}
|-
| {{yes|<code>VMOVDQU32</code>(W0)}} || F || 32 || {{no}} || {{no}}
|-
| rowspan=2 | <code>F2 0F 7F /r</code> || rowspan=2 {{no}} || rowspan=2 {{no}} || {{yes|<code>VMOVDQU16</code>(W1)}} || BW || 16 || {{no}} || {{no}}
|-
| {{yes|<code>VMOVDQU8</code>(W0)}} || BW || 8 || {{no}} || {{no}}
|-
| colspan=2 | Shuffle the four top 16-bit lanes of source vector, then place result in top half of destination vector || {{nowrap|<code>(V)PSHUFHW xmm,xmm/m128,imm8</code>}}{{efn|name="sse41_lane128"|For the <code>VPSHUFLW</code>, <code>VPSHUFHW</code>, <code>VHADDP*</code>, <code>VHSUBP*</code>, <code>VDPPS</code> and <code>VDPPD</code> instructions, encodings with a vector-length wider than 128 bits are available under AVX2 and/or AVX-512, but the operation of such encodings is split into 128-bit lanes where each 128-bit lane internally performs the same operation as the 128-bit variant of the instruction.}} || <code>F3 0F 70 /r ib</code> || {{yes}} || {{yes|Yes{{efn|name=avx_vpshufxw|Under AVX, the <code>VPSHUFHW</code> and <code>VPSHUFLW</code> instructions are only available in 128-bit forms - the 256-bit forms of these instructions require AVX2.}}}} || {{yes}} || BW || 16 || {{no}} || {{no}}
|-
| colspan=2 | Shuffle the four bottom 16-bit lanes of source vector, then place result in bottom half of destination vector || {{nowrap|<code>(V)PSHUFLW xmm,xmm/m128,imm8</code>}}{{efn|name="sse41_lane128"}} || <code>F2 0F 70 /r ib</code> || {{yes}} || {{yes|Yes{{efn|name=avx_vpshufxw}}}} || {{yes}} || BW || 16 || {{no}} || {{no}}
|-
| colspan=2 | Convert packed signed 32-bit integers to FP32 || <code>(V)CVTDQ2PS xmm,xmm/m128</code> || <code>NP 0F 5B /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 32 || {{yes|32}} || RC
|-
| colspan=2 | Convert packed FP32 values to packed signed 32-bit integers || <code>(V)CVTPS2DQ xmm,xmm/m128</code> || <code>66 0F 5B /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 32 || {{yes|32}} || RC
|-
| colspan=2 | Convert packed FP32 values to packed signed 32-bit integers, with round-to-zero || {{nowrap|<code>(V)CVTTPS2DQ xmm,xmm/m128</code>}} || <code>F3 0F 5B /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 32 || {{yes|32}} || SAE
|-
| colspan=2 | Convert packed FP64 values to packed signed 32-bit integers, with round-to-zero || {{nowrap|<code>(V)CVTTPD2DQ xmm,xmm/m64</code>}} || <code>66 0F E6 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}1)}} || F || 32 || {{yes|64}} || SAE
|-
| colspan=2 | Convert packed signed 32-bit integers to FP64 || <code>(V)CVTDQ2PD xmm,xmm/m64</code> || <code>F3 0F E6 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 64 || {{yes|32}} || RC{{efn|For the EVEX-encoded form of <code>VCVTDQ2PD</code>, EVEX embedded rounding controls are permitted but have no effect.}}
|-
| colspan=2 | Convert packed FP64 values to packed signed 32-bit integers || <code>(V)CVTPD2DQ xmm,xmm/m128</code> || <code>F2 0F E6 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}1)}} || F || 32 || {{yes|64}} || RC
|-
! colspan=11 | Added with SSE3
|-
| rowspan=2 | Duplicate floating-point values from even-numbered lanes to next odd-numbered lanes up
| 32-bit || <code>(V)MOVSLDUP xmm,xmm/m128</code> || <code>F3 0F 12 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 32 || {{no}} || {{no}} 
|-
| 64-bit || <code>(V)MOVDDUP xmm/xmm/m128</code> || <code>F2 0F 12 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}1)}} || F || 64 || {{no}} || {{no}}
|-
| colspan=2 | Duplicate FP32 values from odd-numbered lanes to next even-numbered lanes down || <code>(V)MOVSHDUP xmm,xmm/m128</code> || <code>F3 0F 16 /r</code> || {{yes}} || {{yes}} || {{yes|Yes (W{{=}}0)}} || F || 32 || {{no}} || {{no}}
|-
| rowspan=2 | Packed pairwise horizontal addition of floating-point values
| 32-bit || <code>(V)HADDPS xmm,xmm/m128</code>{{efn|name="sse41_lane128"}} || <code>F2 0F 7C /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| 64-bit || <code>(V)HADDPD xmm,xmm/m128</code>{{efn|name="sse41_lane128"}} || <code>66 0F 7C /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 | Packed pairwise horizontal subtraction of floating-point values
| 32-bit || <code>(V)HSUBPS xmm,xmm/m128</code>{{efn|name="sse41_lane128"}} || <code>F2 0F 7D /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}} 
|-
| 64-bit || <code>(V)HSUBPD xmm,xmm/m128</code>{{efn|name="sse41_lane128"}} || <code>66 0F 7D /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 | Packed floating-point add/subtract in alternating lanes. Even-numbered lanes (counting from 0) do subtract, odd-numbered lanes do add.
| {{nowrap|32-bit}} || <code>(V)ADDSUBPS xmm,xmm/m128</code> || <code>F2 0F D0 /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| {{nowrap|64-bit}} || <code>(V)ADDSUBPD xmm,xmm/m128</code> || <code>66 0F D0 /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | Vector load from unaligned memory with looser semantics than <code>(V)MOVDQU</code>.<p>Unlike <code>(V)MOVDQU</code>, it may fetch data more than once or, for a misaligned access, fetch additional data up until the next 16/32-byte alignment boundaries below/above the actually-requested data.</p> || <code>(V)LDDQU xmm,m128</code> || <code>F2 0F F0 /r</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
! colspan=11 | Added with SSE4.1
|-
| colspan=2 | Vector logical test.<p>Sets ZF=1 if bitwise-AND between first operand and second operand results in all-0s, ZF=0 otherwise. Sets CF=1 if bitwise-AND between second operand and bitwise-NOT of first operand results in all-0s, CF=0 otherwise</p>
| <code>(V)PTEST xmm,xmm/m128</code> || <code>66 0F38 17 /r</code> || {{yes}}||{{yes}}||{{no|No{{efn|Opcode not EVEX-encodable. Performing a vector logical test under AVX-512 requires a sequence of at least 2 instructions, e.g. <code>VPTESTMD</code> followed by <code>KORTESTW</code>.}}}}||{{n/a}}||{{n/a}}||{{n/a}}||{{n/a}}
|-
| rowspan=2 | Variable blend packed floating-point values.<p>For each lane of the result, pick the value from either the first or the second argument depending on the top bit of the corresponding lane of <code>XMM0</code>.</p>
| 32-bit || <code>BLENDVPS xmm,xmm/m128</code><br/>{{nowrap|<code>BLENDVPS xmm,xmm/m128,XMM0</code>{{efn|name="blendvp_xmm0"|Assemblers may accept the <code>BLENDVPS</code>/<code>BLENDVPD</code> instructions with or without <code>XMM0</code> as a third argument.}}}} || <code>66 0F38 14 /r</code> || {{yes}} || {{no|No{{efn|name="sse41_blendv"|While AVX does provide <code>VBLENDVPS/VPD</code> instruction that are similar in function to <code>BLENDVPS/VPD</code>, they uses a different opcode and operand encoding - {{nowrap|<code>VEX.66.0F3A.W0 4A/4B /r /is4</code>.}}}}}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| 64-bit || <code>BLENDVPD xmm,xmm/m128</code><br/>{{nowrap|<code>BLENDVPD xmm,xmm/m128,XMM0</code>{{efn|name="blendvp_xmm0"}}}} || <code>66 0F38 15 /r</code> || {{yes}} || {{no|No{{efn|name="sse41_blendv"}}}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 | Rounding of packed floating-point values to integer.<p>Rounding mode specified by imm8 argument.</p>
| 32-bit || {{nowrap|<code>(V)ROUNDPS xmm,xmm/m128,imm8</code>}} || <code>66 0F3A 08 /r ib</code> || {{yes}} || {{yes}} || {{no|No{{efn|name="sse41_rndscale"|Opcode not available under AVX-512. Instead, AVX512F provides different opcodes - {{nowrap|<code>EVEX.66.0F3A (08..0B) /r ib</code>}} - for its new <code>VRNDSCALE*</code> rounding instructions.}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| 64-bit || {{nowrap|<code>(V)ROUNDPD xmm,xmm/m128,imm8</code>}} || <code>66 0F3A 09 /r ib</code> || {{yes}} || {{yes}} || {{no|No{{efn|name="sse41_rndscale"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 | Rounding of scalar floating-point value to integer.
| 32-bit || {{nowrap|<code>(V)ROUNDSS xmm,xmm/m128,imm8</code>}} || <code>66 0F3A 0A /r ib</code> || {{yes}} || {{yes}} || {{no|No{{efn|name="sse41_rndscale"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| 64-bit || {{nowrap|<code>(V)ROUNDSD xmm,xmm/m128,imm8</code>}} || <code>66 0F3A 0B /r ib</code> || {{yes}} || {{yes}} || {{no|No{{efn|name="sse41_rndscale"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 | Blend packed floating-point values. For each lane of the result, pick the value from either the first or the second argument depending on the corresponding imm8 bit.
| 32-bit || <code>(V)BLENDPS xmm,xmm/m128,imm8</code> || <code>66 0F3A 0C /r ib</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| 64-bit || {{nowrap|<code>(V)BLENDPD xmm,xmm/m128,imm8</code>}} || {{nowrap|<code>66 0F3A 0D /r ib</code>}} || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | Extract 32-bit lane of XMM register to general-purpose register or memory location.<p>Bits[1:0] of imm8 is used to select lane.</p> || <code>(V)EXTRACTPS r/m32,xmm,imm8</code> || <code>66 0F3A 17 /r ib</code> || {{yes}} || {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0)}} || F || {{no}} || {{no}} || {{no}}
|-
| colspan=2 | Obtain 32-bit value from source XMM register or memory, and insert into the specified lane of destination XMM register.<p>
If the source argument is an XMM register, then bits[7:6] of the imm8 is used to select which 32-bit lane to select source from, otherwise the specified 32-bit memory value is used. This 32-bit value is then inserted into the destination register lane specified by bits[5:4] of the imm8. After insertion, each 32-bit lane of the destination register may optionally be zeroed out - bits[3:0] of the imm8 provides a bitmap of which lanes to zero out.</p>
| {{nowrap|<code>(V)INSERTPS xmm,xmm/m32,imm8</code>}} || <code>66 0F3A 21 /r ib</code> || {{yes}} || {{yes|Yes (L{{=}}0)}} || {{yes|Yes (L{{=}}0,W{{=}}0)}} || F || {{no}} || {{no}} || {{no}}
|-
| colspan=2 | 4-component dot-product of 32-bit floating-point values.<p>Bits [7:4] of the imm8 specify which lanes should participate in the dot-product, bits[3:0] specify which lanes in the result should receive the dot-product (remaining lanes are filled with zeros)</p> || {{nowrap|<code>(V)DPPS xmm,xmm/m128,imm8</code>}}{{efn|name="sse41_lane128"}} || <code>66 0F3A 40 /r ib</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| colspan=2 | 2-component dot-product of 64-bit floating-point values.<p>Bits [5:4] of the imm8 specify which lanes should participate in the dot-product, bits[1:0] specify which lanes in the result should receive the dot-product (remaining lanes are filled with zeros) </p> || {{nowrap|<code>(V)DPPD xmm,xmm/m128,imm8</code>}}{{efn|name="sse41_lane128"}} || <code>66 0F3A 41 /r ib</code> || {{yes}} || {{yes}} || {{no}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
! colspan=11 | Added with SSE4a (AMD only)
|-
| rowspan=2 colspan=2 | 64-bit bitfield insert, using the low 64 bits of XMM registers.<p>First argument is an XMM register to insert bitfield into, second argument is a source register containing the bitfield to insert (starting from bit 0).</p><p>For the 4-argument version, the first imm8 specifies bitfield length and the second imm8 specifies bit-offset to insert bitfield at. For the 2-argument version, the length and offset are instead taken from bits [69:64] and [77:72] of the second argument, respectively.</p> || <code>INSERTQ xmm,xmm,imm8,imm8</code> || {{nowrap|<code>F2 0F 78 /r ib ib</code>}} || {{yes}} ||{{no}}||{{no|No{{efn|name="sse41_sse4a_evex"|Under AVX-512, EVEX-encoding the <code>INSERTQ</code>/<code>EXTRQ</code> opcodes result in AVX-512 instructions completely unrelated to SSE4a, namely <code>VCVT(T)P(S{{!}}D)2UQQ</code> and <code>VCVT(T)S(S{{!}}D)2USI</code>.}}}}  || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| <code>INSERTQ xmm,xmm</code> || <code>F2 0F 79 /r</code> || {{yes}} ||{{no}}||{{no|No{{efn|name="sse41_sse4a_evex"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| rowspan=2 colspan=2 | 64-bit bitfield extract, from the lower 64 bits of an XMM register.<p>The first argument serves as both source that bitfield is extracted from and destination that bitfield is written to.</p><p>For the 3-argument version, the first imm8 specifies bitfield length and the second imm8 specifies bitfield bit-offset. For the 2-argument version, the second argument is an XMM register that contains bitfield length at bits[5:0] and bit-offset at bits[13:8].</p> || <code>EXTRQ xmm,imm8,imm8</code> || <code>66 0F 78 /0 ib ib</code> || {{yes}} ||{{no}}||{{no|No{{efn|name="sse41_sse4a_evex"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|-
| <code>EXTRQ xmm,xmm</code> || <code>66 0F 79 /r</code> || {{yes}} ||{{no}}||{{no|No{{efn|name="sse41_sse4a_evex"}}}} || {{n/a}} || {{n/a}} || {{n/a}} || {{n/a}}
|}
{{notelist}}
{{vpad}}





== [[Advanced Vector Extensions|AVX]] ==
[[Advanced Vector Extensions|AVX]] were first supported by Intel with Sandy Bridge and by AMD with [[AMD Bulldozer|Bulldozer]].

Vector operations on 256 bit registers.

{| class="wikitable sortable"
! Instruction
! Description
|-
| VBROADCASTSS
| rowspan=3 | Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.
|-
| VBROADCASTSD
|-
| VBROADCASTF128
|-
| VINSERTF128
| Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
|-
| VEXTRACTF128
| Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
|-
| VMASKMOVPS
| rowspan=2 | Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. On the AMD Jaguar processor architecture, this instruction with a memory source operand takes more than 300 clock cycles when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw.<ref>{{cite web |url=http://www.agner.org/optimize/microarchitecture.pdf |title=The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers and compiler makers |access-date=October 17, 2016}}</ref>
|-
| VMASKMOVPD
|-
| VPERMILPS
| rowspan=2 | Permute In-Lane. Shuffle the 32-bit or 64-bit vector elements of one input operand. These are in-lane 256-bit instructions, meaning that they operate on all 256 bits with two separate 128-bit shuffles, so they can not shuffle across the 128-bit lanes.<ref>{{cite web |url=https://chessprogramming.wikispaces.com/AVX2 |title=Chess programming AVX2 |access-date=October 17, 2016 |archive-date=July 10, 2017 |archive-url=https://web.archive.org/web/20170710034021/http://chessprogramming.wikispaces.com/AVX2 |url-status=dead }}</ref>
|-
| VPERMILPD
|-
| VPERM2F128
| Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
|-
| VZEROALL
| Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.
|-
| VZEROUPPER
| Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.
|}

=== [[F16C]] ===
Half-precision floating-point conversion.

{| class="wikitable sortable"
! Instruction !! Meaning
|-
| {{mono|VCVTPH2PS xmmreg,xmmrm64}} || Convert four half-precision floating point values in memory or the bottom half of an XMM register to four single-precision floating-point values in an XMM register
|-
| {{mono|VCVTPH2PS ymmreg,xmmrm128}} || Convert eight half-precision floating point values in memory or an XMM register (the bottom half of a YMM register) to eight single-precision floating-point values in a YMM register
|-
| {{mono|VCVTPS2PH xmmrm64,xmmreg,imm8}} || Convert four single-precision floating point values in an XMM register to half-precision floating-point values in memory or the bottom half an XMM register
|-
| {{nowrap|{{mono|VCVTPS2PH xmmrm128,ymmreg,imm8}}}} || Convert eight single-precision floating point values in a YMM register to half-precision floating-point values in memory or an XMM register
|}

== [[AVX2]] ==
Introduced in Intel's [[Haswell (microarchitecture)|Haswell microarchitecture]] and AMD's [[Excavator (microarchitecture)|Excavator]].

Expansion of most vector integer SSE and AVX instructions to 256 bits

{| class="wikitable sortable"
! Instruction
! Description
|-
| VBROADCASTSS
| rowspan=2 | Copy a 32-bit or 64-bit register operand to all elements of a XMM or YMM vector register. These are register versions of the same instructions in AVX1. There is no 128-bit version however, but the same effect can be simply achieved using VINSERTF128.
|-
| VBROADCASTSD
|-
| VPBROADCASTB
| rowspan=4 | Copy an 8, 16, 32 or 64-bit integer register or memory operand to all elements of a XMM or YMM vector register.
|-
| VPBROADCASTW
|-
| VPBROADCASTD
|-
| VPBROADCASTQ
|-
| VBROADCASTI128
| Copy a 128-bit memory operand to all elements of a YMM vector register.
|-
| VINSERTI128
| Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.
|-
| VEXTRACTI128
| Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.
|-
| VGATHERDPD
| rowspan=4 | [[Gather-scatter (vector addressing)|Gathers]] single or double precision floating point values using either 32 or 64-bit indices and scale.
|-
| VGATHERQPD
|-
| VGATHERDPS
|-
| VGATHERQPS
|-
| VPGATHERDD
| rowspan=4 | Gathers 32 or 64-bit integer values using either 32 or 64-bit indices and scale.
|-
| VPGATHERDQ
|-
| VPGATHERQD
|-
| VPGATHERQQ
|-
| VPMASKMOVD
| rowspan=2 | Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.
|-
| VPMASKMOVQ
|-
| VPERMPS
| rowspan=2 | Shuffle the eight 32-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
|-
| VPERMD
|-
| VPERMPD
| rowspan=2 | Shuffle the four 64-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.
|-
| VPERMQ
|-
| VPERM2I128
| Shuffle (two of) the four 128-bit vector elements of ''two'' 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.
|-
| VPBLENDD
| Doubleword immediate version of the PBLEND instructions from [[SSE4]].
|-
| VPSLLVD
| rowspan=2 | Shift left logical. Allows variable shifts where each element is shifted according to the packed input.
|-
| VPSLLVQ
|-
| VPSRLVD
| rowspan=2 | Shift right logical. Allows variable shifts where each element is shifted according to the packed input.
|-
| VPSRLVQ
|-
| VPSRAVD
| Shift right arithmetically. Allows variable shifts where each element is shifted according to the packed input.
|}

== FMA3 and FMA4 instructions ==
{{Main|FMA instruction set}}
Floating-point [[fused multiply-add]] instructions are introduced in x86 as two instruction set extensions, "FMA3" and "FMA4", both of which build on top of [[Advanced Vector Extensions|AVX]] to provide a set of scalar/vector instructions using the xmm/ymm/zmm vector registers. FMA3 defines a set of 3-operand fused-multiply-add instructions that take three input operands and writes its result back to the first of them. FMA4 defines a set of 4-operand fused-multiply-add instructions that take four input operands – a destination operand and three source operands.

FMA3 is supported on Intel CPUs starting with [[Haswell (microarchitecture)|Haswell]], on AMD CPUs starting with [[Piledriver (microarchitecture)|Piledriver]], and on [[Zhaoxin]] CPUs starting with YongFeng. FMA4 was only supported on AMD [[Bulldozer (microarchitecture)|Family 15h (Bulldozer)]] CPUs and has been abandoned from [[AMD Zen]] onwards. The FMA3/FMA4 extensions are not considered to be an intrinsic part of AVX or AVX2, although all Intel and AMD (but not Zhaoxin) processors that support AVX2 also support FMA3. FMA3 instructions (in EVEX-encoded form) are, however, [[AVX-512]] foundation instructions.
<br />
The FMA3 and FMA4 instruction sets both define a set of 10 fused-multiply-add operations, all available in FP32 and FP64 variants. For each of these variants, FMA3 defines three operand orderings while FMA4 defines two.
<br />
'''FMA3 encoding'''
<br />
FMA3 instructions are encoded with the [[VEX prefix|VEX]] or [[EVEX prefix]]es – on the form <code>VEX.66.0F38 <b>xy</b> /r</code> or <code>EVEX.66.0F38 <b>xy</b> /r</code>. The VEX.W/EVEX.W bit selects floating-point format (W=0 means [[FP32]], W=1 means [[FP64]]). The opcode byte <code><b>xy</b></code> consists of two nibbles, where the top nibble <code><b>x</b></code> selects operand ordering (<code>9</code>='132', <code>A</code>='213', <code>B</code>='231') and the bottom nibble <code><b>y</b></code> (values 6..F) selects which one of the 10 fused-multiply-add operations to perform. (<code><b>x</b></code> and <code><b>y</b></code> outside the given ranges will result in something that is not an FMA3 instruction.)
<br />
At the assembly language level, the operand ordering is specified in the mnemonic of the instruction:
* <code>vfmadd<b>132</b>sd xmm1,xmm2,xmm3</code> will perform <code>xmm1 ← (xmm<b>1</b>*xmm<b>3</b>)+xmm<b>2</b></code>
* <code>vfmadd<b>213</b>sd xmm1,xmm2,xmm3</code> will perform <code>xmm1 ← (xmm<b>2</b>*xmm<b>1</b>)+xmm<b>3</b></code>
* <code>vfmadd<b>231</b>sd xmm1,xmm2,xmm3</code> will perform <code>xmm1 ← (xmm<b>2</b>*xmm<b>3</b>)+xmm<b>1</b></code>
For all FMA3 variants, the first two arguments must be xmm/ymm/zmm vector register arguments, while the last argument may be either a vector register or memory argument. Under AVX-512 and AVX10, the EVEX-encoded variants support EVEX-prefix-encoded broadcast, opmasks and rounding-controls.
<br />
The AVX512-FP16 extension, introduced in [[Sapphire Rapids]], adds [[FP16]] variants of the FMA3 instructions – these all take the form <code>EVEX.66.MAP6.W0 <b>xy</b> /r</code> with the opcode byte working in the same way as for the FP32/FP64 variants. The AVX10.2 extension, published in 2024,<ref>Intel, [https://cdrdv2-public.intel.com/828965/361050-intel-avx10.2-spec.pdf Advanced Vector Extensions 10.2 Architecture Specification], order no. 361050-001, rev 1.0, July 2024. [https://web.archive.org/web/20240801165629/https://cdrdv2-public.intel.com/828965/361050-intel-avx10.2-spec.pdf Archived] on 1 Aug 2024.</ref> similarly adds [[BF16]] variants of the packed (but not scalar) FMA3 instructions – these all take the form <code>EVEX.NP.MAP6.W0 <b>xy</b> /r</code> with the opcode byte again working similar to the FP32/FP64 variants.
(For the FMA4 instructions, no FP16 or BF16 variants are defined.)
<br />
'''FMA4 encoding'''
<br />
FMA4 instructions are encoded with the VEX prefix, on the form <code>VEX.66.0F3A <b>xx</b> /r ib</code> (no EVEX encodings are defined). The opcode byte <code><b>xx</b></code> uses its bottom bit to select floating-point format (0=FP32, 1=FP64) and the remaining bits to select one of the 10 fused-multiply-add operations to perform.

For FMA4, operand ordering is controlled by the VEX.W bit. If VEX.W=0, then the third operand is the r/m operand specified by the instruction's [[ModR/M]] byte and the fourth operand is a register operand, specified by bits 7:4 of the ''ib'' (8-bit immediate) part of the instruction. If VEX.W=1, then these two operands are swapped. For example:
* <code>vfmaddsd xmm1,xmm2,[mem],xmm3</code> will perform <code>xmm1 ← (xmm2*[mem])+xmm3</code> and require a W=0 encoding.
* <code>vfmaddsd xmm1,xmm2,xmm3,[mem]</code> will perform <code>xmm1 ← (xmm2*xmm3)+[mem]</code> and require a W=1 encoding.
* <code>vfmaddsd xmm1,xmm2,xmm3,xmm4</code> will perform <code>xmm1 ← (xmm2*xmm3)+xmm4</code> and can be encoded with either W=0 or W=1.
<br />
'''Opcode table'''
<br />
The 10 fused-multiply-add operations and the 122 instruction variants they give rise to are given by the following table – with FMA4 instructions highlighted with * and yellow cell coloring, and FMA3 instructions not highlighted:

{|class="wikitable sortable"
! Basic operation !! Opcode byte !! FP32 instructions !! FP64 instructions !! FP16 instructions<br/>(AVX512-FP16) !! BF16 instructions<br/>(AVX10.2)
|-
| rowspan=4 | Packed alternating multiply-add/subtract<br /><ul><li>''(A*B)-C'' in even-numbered lanes{{efn|Vector register lanes are counted from 0 upwards in a [[little-endian]] manner – the lane that contains the first byte of the vector is considered to be even-numbered.}}<li>''(A*B)+C'' in odd-numbered lanes</ul>
| <code>96</code> || <code>VFMADDSUB132PS</code> || <code>VFMADDSUB132PD</code> || <code>VFMADDSUB132PH</code> || {{n/a}}
|-
| <code>A6</code> || <code>VFMADDSUB213PS</code> || <code>VFMADDSUB213PD</code> || <code>VFMADDSUB213PH</code> || {{n/a}}
|-
| <code>B6</code> || <code>VFMADDSUB231PS</code> || <code>VFMADDSUB231PD</code> || <code>VFMADDSUB231PH</code> || {{n/a}}
|-
| {{maybe|<code>5C/5D</code>*}} || {{maybe|<code>VFMADDSUBPS</code>*}} || {{maybe|<code>VFMADDSUBPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Packed alternating multiply-subtract/add<br /><ul><li>''(A*B)+C'' in even-numbered lanes<li>''(A*B)-C'' in odd-numbered lanes</ul>
| <code>97</code> || <code>VFMSUBADD132PS</code> || <code>VFMSUBADD132PD</code> || <code>VFMSUBADD132PH</code> || {{n/a}}
|-
| <code>A7</code> || <code>VFMSUBADD213PS</code> || <code>VFMSUBADD213PD</code> || <code>VFMSUBADD213PH</code> || {{n/a}}
|-
| <code>B7</code> || <code>VFMSUBADD231PS</code> || <code>VFMSUBADD231PD</code> || <code>VFMSUBADD231PH</code> || {{n/a}}
|-
| {{maybe|<code>5E/5F</code>*}} || {{maybe|<code>VFMSUBADDPS</code>*}} || {{maybe|<code>VFMSUBADDPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Packed multiply-add<br />''(A*B)+C''
| <code>98</code> || <code>VFMADD132PS</code> || <code>VFMADD132PD</code> || <code>VFMADD132PH</code> || <code>VFMADD132BF16</code>
|-
| <code>A8</code> || <code>VFMADD213PS</code> || <code>VFMADD213PD</code> || <code>VFMADD213PH</code> || <code>VFMADD213BF16</code>
|-
| <code>B8</code> || <code>VFMADD231PS</code> || <code>VFMADD231PD</code> || <code>VFMADD231PH</code> || <code>VFMADD231BF16</code>
|-
| {{maybe|<code>68/69</code>*}} || {{maybe|<code>VFMADDPS</code>*}} || {{maybe|<code>VFMADDPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Scalar multiply-add<br />''(A*B)+C''
| <code>99</code> || <code>VFMADD132SS</code> || <code>VFMADD132SD</code> || <code>VFMADD132SH</code> || {{n/a}}
|-
| <code>A9</code> || <code>VFMADD213SS</code> || <code>VFMADD213SD</code> || <code>VFMADD213SH</code> || {{n/a}}
|-
| <code>B9</code> || <code>VFMADD231SS</code> || <code>VFMADD231SD</code> || <code>VFMADD231SH</code> || {{n/a}}
|-
| {{maybe|<code>6A/6B</code>*}} || {{maybe|<code>VFMADDSS</code>*}} || {{maybe|<code>VFMADDSD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Packed multiply-subtract<br />''(A*B)-C''
| <code>9A</code> || <code>VFMSUB132PS</code> || <code>VFMSUB132PD</code> || <code>VFMSUB132PH</code> || <code>VFMSUB132BF16</code>
|-
| <code>AA</code> || <code>VFMSUB213PS</code> || <code>VFMSUB213PD</code> || <code>VFMSUB213PH</code> || <code>VFMSUB213BF16</code>
|-
| <code>BA</code> || <code>VFMSUB231PS</code> || <code>VFMSUB231PD</code> || <code>VFMSUB231PH</code> || <code>VFMSUB231BF16</code>
|-
| {{maybe|<code>6C/6D</code>*}} || {{maybe|<code>VFMSUBPS</code>*}} || {{maybe|<code>VFMSUBPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Scalar multiply-subtract<br />''(A*B)-C''
| <code>9B</code> || <code>VFMSUB132SS</code> || <code>VFMSUB132SD</code> || <code>VFMSUB132SH</code> || {{n/a}}
|-
| <code>AB</code> || <code>VFMSUB213SS</code> || <code>VFMSUB213SD</code> || <code>VFMSUB213SH</code> || {{n/a}}
|-
| <code>BB</code> || <code>VFMSUB231SS</code> || <code>VFMSUB231SD</code> || <code>VFMSUB231SH</code> || {{n/a}}
|-
| {{maybe|<code>6E/6F</code>*}} || {{maybe|<code>VFMSUBSS</code>*}} || {{maybe|<code>VFMSUBSD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Packed negative-multiply-add<br />''(-A*B)+C''
| <code>9C</code> || <code>VFNMADD132PS</code> || <code>VFNMADD132PD</code> || <code>VFNMADD132PH</code> || <code>VFNMADD132BF16</code>
|-
| <code>AC</code> || <code>VFNMADD213PS</code> || <code>VFNMADD213PD</code> || <code>VFNMADD213PH</code> || <code>VFNMADD213BF16</code>
|-
| <code>BC</code> || <code>VFNMADD231PS</code> || <code>VFNMADD231PD</code> || <code>VFNMADD231PH</code> || <code>VFNMADD231BF16</code>
|-
| {{maybe|<code>78/79</code>*}} || {{maybe|<code>VFMADDPS</code>*}} || {{maybe|<code>VFMADDPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Scalar negative-multiply-add<br />''(-A*B)+C''
| <code>9D</code> || <code>VFMADD132SS</code> || <code>VFMADD132SD</code> || <code>VFMADD132SH</code> || {{n/a}}
|-
| <code>AD</code> || <code>VFMADD213SS</code> || <code>VFMADD213SD</code> || <code>VFMADD213SH</code> || {{n/a}}
|-
| <code>BD</code> || <code>VFMADD231SS</code> || <code>VFMADD231SD</code> || <code>VFMADD231SH</code> || {{n/a}}
|-
| {{maybe|<code>7A/7B</code>*}} || {{maybe|<code>VFMADDSS</code>*}} || {{maybe|<code>VFMADDSD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Packed negative-multiply-subtract<br />''(-A*B)-C''
| <code>9E</code> || <code>VFNMSUB132PS</code> || <code>VFNMSUB132PD</code> || <code>VFNMSUB132PH</code> || <code>VFNMSUB132BF16</code>
|-
| <code>AE</code> || <code>VFNMSUB213PS</code> || <code>VFNMSUB213PD</code> || <code>VFNMSUB213PH</code> || <code>VFNMSUB213BF16</code>
|-
| <code>BE</code> || <code>VFNMSUB231PS</code> || <code>VFNMSUB231PD</code> || <code>VFNMSUB231PH</code> || <code>VFNMSUB231BF16</code>
|-
| {{maybe|<code>7C/7D</code>*}} || {{maybe|<code>VFNMSUBPS</code>*}} || {{maybe|<code>VFNMSUBPD</code>*}} || {{n/a}} || {{n/a}}
|-
| rowspan=4 | Scalar negative-multiply-subtract<br />''(-A*B)-C''
| <code>9F</code> || <code>VFNMSUB132SS</code> || <code>VFNMSUB132SD</code> || <code>VFNMSUB132SH</code> || {{n/a}}
|-
| <code>AF</code> || <code>VFNMSUB213SS</code> || <code>VFNMSUB213SD</code> || <code>VFNMSUB213SH</code> || {{n/a}}
|-
| <code>BF</code> || <code>VFNMSUB231SS</code> || <code>VFNMSUB231SD</code> || <code>VFNMSUB231SH</code> || {{n/a}}
|-
| {{maybe|<code>7E/7F</code>*}} || {{maybe|<code>VFNMSUBSS</code>*}} || {{maybe|<code>VFNMSUBSD</code>*}} || {{n/a}} || {{n/a}}
|}
{{notelist}}

== AVX-512 ==
{{Main|AVX-512#New instructions by sets}}
[[AVX-512]], introduced in 2014, adds 512-bit wide vector registers (extending the 256-bit registers, which become the new registers' lower halves) and doubles their count to 32; the new registers are thus named zmm0 through zmm31. It adds eight mask registers, named k0 through k7, which may be used to restrict operations to specific parts of a vector register. Unlike previous instruction set extensions, AVX-512 is implemented in several groups; only the foundation ("AVX-512F") extension is mandatory.<ref>{{cite web |title=Intel AVX-512 Instructions |url=https://www.intel.com/content/www/us/en/developer/articles/technical/intel-avx-512-instructions.html |website=Intel |access-date=21 June 2022 |language=en}}</ref>  Most of the added instructions may also be used with the 256- and 128-bit registers.

== AMX ==
{{Main|Advanced Matrix Extensions}}
Intel AMX adds eight new tile-registers, <code>tmm0</code>-<code>tmm7</code>, each holding a [[Matrix (mathematics)|matrix]], with a maximum capacity of 16 rows of 64 bytes per tile-register. It also adds a <code>TILECFG</code> register to configure the sizes of the actual matrices held in each of the eight tile-registers, and a set of instructions to perform [[matrix multiplication]]s on these registers.

{| class="wikitable sortable"
! AMX subset !! Instruction mnemonics !! Opcode !! Instruction description !! Added in
|-
! colspan=5 |
|-
| rowspan=7 | {{glossary}}{{term|AMX-TILE}}{{defn|AMX control and tile management.}}{{glossary end}}
| <code>LDTILECFG m512</code> || <code>VEX.128.NP.0F38.W0 49 /0</code> || Load AMX tile configuration data structure from memory as a 64-byte data structure.
| rowspan=14 | {{nowrap|[[Sapphire Rapids]]}}
|-
| <code>STTILECFG m512</code> || <code>VEX.128.66.0F38 W0 49 /0</code> || Store AMX tile configuration data structure to memory.
|-
| <code>TILERELEASE</code> || <code>VEX.128.NP.0F38.W0 49 C0</code> || Initialize <code>TILECFG</code> and tile data registers (<code>tmm0</code> to <code>tmm7</code>) to the INIT state (all-zeroes).
|-
| <code>TILEZERO tmm</code> || {{nowrap|<code>VEX.128.F2.0F38.W0 49 /r</code>{{efn|text=For <code>TILEZERO</code>, the tile-register to clear is specified by bits 5:3 of the instruction's [[ModR/M]] byte. Bits 7:6 must be set to 11b, and bits 2:0 must be set to 000b.}}}} || Zero out contents of one tile register.
|-
| <code>TILELOADD tmm, sibmem</code> || {{nowrap|<code>VEX.128.F2.0F38.W0 4B /r</code>{{efn|name=amx_sibmem|text=For the <code>TILELOADD</code>, <code>TILELOADDT1</code> and <code>TILESTORED</code> instructions, the memory argument must use a memory addressing mode with the SIB-byte. Under this addressing mode, the base register and displacement are used to specify the starting address for the first row of the tile to load/store from/to memory – the scale and index are used to specify a per-row stride.<br />These instructions are all interruptible – an interrupt or memory exception taken in the middle of these instructions will cause progress tracking information to be written to <code>TILECFG.start_row</code>, so that the instruction may continue on a partially-loaded/stored tile after the interruption.}}}} || Load a data tile from memory into AMX tile register.
|-
| {{nowrap|<code>TILELOADDT1 tmm, sibmem</code>}} || <code>VEX.128.66.0F38.W0 4B /r</code>{{efn|name=amx_sibmem}} || Load a data tile from memory into AMX tile register, with a hint that data should not be kept in the nearest cache levels.
|-
| <code>TILESTORED mem, sibtmm</code> || <code>VEX.128.F3.0F38.W0 4B /r</code>{{efn|name=amx_sibmem}} || Store a data tile to memory from AMX tile register.
|-
! colspan=4 |
|-
| rowspan=4 | {{glossary}}{{term|AMX-INT8}}{{defn|Matrix multiplication of tiles, with source data interpreted as 8-bit integers and destination data accumulated as 32-bit integers.}}{{glossary end}}
| <code>TDPBSSD tmm1,tmm2,tmm3</code>{{efn|name=amx_mul|For all of the AMX matrix multiply instructions, the three arguments are required to be three different tile registers, or else the instruction will #UD.}} || <code>VEX.128.F2.0F38.W0 5E /r</code> || Matrix multiply signed bytes from tmm2 with signed bytes from tmm3, accumulating result in tmm1.
|-
| <code>TDPBSUD tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}} || <code>VEX.128.F3.0F38.W0 5E /r</code> || Matrix multiply signed bytes from tmm2 with unsigned bytes from tmm3, accumulating result in tmm1.
|-
| <code>TDPBUSD tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}} || <code>VEX.128.66.0F38.W0 5E /r</code> || Matrix multiply unsigned bytes from tmm2 with signed bytes from tmm3, accumulating result in tmm1.
|-
| <code>TDPBUUD tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}} || <code>VEX.128.NP.0F38.W0 5E /r</code> || Matrix multiply unsigned bytes from tmm2 with unsigned bytes from tmm3, accumulating result in tmm1.
|-
! colspan=4 |
|-
| {{glossary}}{{term|AMX-BF16}}{{defn|Matrix multiplication of tiles, with source data interpreted as [[bfloat16]] values, and destination data accumulated as [[FP32]] floating-point values.}}{{glossary end}}
| <code>TDPBF16PS tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}}|| <code>VEX.128.F3.0F38.W0 5C /r</code> || Matrix multiply BF16 values from tmm2 with BF16 values from tmm3, accumulating result in tmm1.
|-
! colspan=5 |
|-
| {{glossary}}{{term|AMX-FP16}}{{defn|Matrix multiplication of tiles, with source data interpreted as [[FP16]] values, and destination data accumulated as [[FP32]] floating-point values.}}{{glossary end}}
| <code>TDPFP16PS tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}} || <code>VEX.128.F2.0F38.W0 5C /r</code> || Matrix multiply FP16 values from tmm2 with FP16 values from tmm3, accumulating result in tmm1.
| ([[Granite Rapids]])
|-
! colspan=5 |
|-
| rowspan=2 | {{glossary}}{{term|AMX-COMPLEX}}{{defn|Matrix multiplication of tiles, with source data interpreted as [[complex number]]s represented as pairs of [[FP16]] values, and destination data accumulated as [[FP32]] floating-point values.}}{{glossary end}}
| {{nowrap|<code>TCMMRLFP16PS tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}}}} || <code>VEX.128.NP.0F38.W0 6C /r</code> || Matrix multiply complex numbers from tmm2 with complex numbers from tmm3, accumulating real part of result in tmm1.
| rowspan=2 | {{nowrap|([[Granite Rapids]] D)}}
|-
| {{nowrap|<code>TCMMILFP16PS tmm1,tmm2,tmm3</code>{{efn|name=amx_mul}}}} || <code>VEX.128.66.0F38.W0 6C /r</code> || Matrix multiply complex numbers from tmm2 with complex numbers from tmm3, accumulating imaginary part of result in tmm1.
|}
{{notelist}}

== See also ==
* [[x86 instruction listings]]
* [[List of discontinued x86 instructions]]
* [[ARM architecture family#64/32-bit architecture]]

== References ==
{{reflist}}

== External links ==

* [https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html Intel Intrinsics Guide] - searchable reference for Intel MMX/SSE/AVX/AVX512 SIMD [[Intrinsic function|intrinsics]]

[[Category:X86 instructions| ]]
[[Category:Instruction set listings]]