View source for Word (computer architecture)

{{Short description|Base memory unit handled by a computer}}
{{Use dmy dates|date=August 2019|cs1-dates=y}}
{{Computer architecture bit widths}}
{{more footnotes|date=July 2023}}
{{redirect-distinguish|qword|Question word}}
In [[computing]], a '''word''' is any [[Central processing unit|processor]] design's natural unit of data. A word is a fixed-sized [[Data (computing)|datum]] handled as a unit by the [[instruction set]] or the hardware of the processor. The number of [[bit]]s or digits{{efn|Many early computers were [[Decimal computer|decimal]], and a few were [[ternary computer|ternary]]}} in a word (the ''word size'', ''word width'', or ''word length'') is an important characteristic of any specific processor design or [[computer architecture]].

The size of a word is reflected in many aspects of a computer's structure and operation; the majority of the [[processor register|registers]] in a processor are usually word-sized and the largest datum that can be transferred to and from the [[computer memory|working memory]] in a single operation is a word in many (not all) architectures. The largest possible [[Memory address|address]] size, used to designate a location in memory, is typically a hardware word (here, "hardware word" means the full-sized natural word of the processor, as opposed to any other definition used).

Documentation for older computers with fixed word size commonly states memory sizes in words rather than bytes or characters.  The documentation sometimes uses [[metric prefix]]es correctly, sometimes with rounding, e.g., ''65 kilowords'' (kW) meaning for 65536 words, and sometimes uses them incorrectly, with ''kilowords'' (kW) meaning 1024 words (2<sup>10</sup>) and megawords (MW) meaning 1,048,576 words (2<sup>20</sup>). With standardization on 8-bit bytes and byte addressability, stating memory sizes in bytes, kilobytes, and megabytes with powers of 1024 rather than 1000 has become the norm, although there is some use of the [[International Electrotechnical Commission|IEC]] [[binary prefix]]es.

Several of the earliest computers (and a few modern as well) use [[binary-coded decimal]] rather than plain [[Binary number|binary]], typically having a word size of 10 or 12 [[decimal]] digits, and some early [[decimal computer]]s have no fixed word length at all. Early binary systems tended to use word lengths that were some multiple of 6-bits, with the 36-bit word being especially common on [[mainframe computer]]s. The introduction of [[ASCII]] led to the move to systems with word lengths that were a multiple of 8-bits, with 16-bit machines being popular in the 1970s before the move to modern processors with 32 or 64 bits.<ref name="Beebe_2017"/> Special-purpose designs like [[digital signal processor]]s, may have any word length from 4 to 80 bits.<ref name="Beebe_2017"/>

The size of a word can sometimes differ from the expected due to [[backward compatibility]] with earlier computers. If multiple compatible variations or a family of processors share a common architecture and instruction set but differ in their word sizes, their documentation and software may become notationally complex to accommodate the difference (see [[#Size families|Size families]] below).

== Uses of words ==
Depending on how a computer is organized, word-size units may be used for:
;Fixed-point numbers: Holders for [[fixed-point arithmetic|fixed point]], usually [[integer (computer science)|integer]], numerical values may be available in one or in several different sizes, but one of the sizes available will almost always be the word. The other sizes, if any, are likely to be multiples or fractions of the word size. The smaller sizes are normally used only for efficient use of memory; when loaded into the processor, their values usually go into a larger, word sized holder.
;Floating-point numbers: Holders for [[floating-point arithmetic|floating-point]] numerical values are typically either a word or a multiple of a word.
;Addresses: Holders for memory addresses must be of a size capable of expressing the needed range of values but not be excessively large, so often the size used is the word though it can also be a multiple or fraction of the word size.
;Registers: [[Processor register]]s are designed with a size appropriate for the type of data they hold, e.g. integers, floating-point numbers, or addresses. Many computer architectures use [[general-purpose register]]s that are capable of storing data in multiple representations.
;{{anchor|Catena}}Memory–processor transfer: When the processor reads from the memory subsystem into a register or writes a register's value to memory, the amount of data transferred is often a word. Historically, this amount of bits which could be transferred in one cycle was also called a ''catena'' in some environments (such as the [[Bull Gamma 60]]).<ref name="Dreyfus_1958_Gamma60"/><ref name="Buchholz_1962"/> In simple memory subsystems, the word is transferred over the memory [[Bus (computing)|data bus]], which typically has a width of a word or half-word. In memory subsystems that use [[CPU cache|caches]], the word-sized transfer is the one between the processor and the first level of cache; at lower levels of the [[memory hierarchy]] larger transfers (which are a multiple of the word size) are normally used.
;Unit of address resolution: In a given architecture, successive address values almost{{efn|The UNIVAC 1005 addresses core using 5-bit [[Gray code]]s for row and column.}} always designate successive units of memory; this unit is the unit of address resolution. In most computers, the unit is either a character (e.g. a byte) or a word. (A few computers have used bit resolution.) If the unit is a word, then a larger amount of memory can be accessed using an address of a given size at the cost of added complexity to access individual characters. On the other hand, if the unit is a byte, then individual characters can be addressed (i.e. selected during the memory operation).
;Instructions: [[Machine instruction]]s are normally the size of the architecture's word, such as in [[RISC architectures]], or a multiple of the "char" size that is a fraction of it. This is a natural choice since instructions and data usually share the same memory subsystem. In [[Harvard architecture]]s the word sizes of instructions and data need not be related, as instructions and data are stored in different memories; for example, [[1ESS switch#1ESS computer|the processor in the 1ESS electronic telephone switch]] has 37-bit instructions and 23-bit data words.

== Word size choice ==
When a computer architecture is designed, the choice of a word size is of substantial importance.  There are design considerations which encourage particular bit-group sizes for particular uses (e.g. for addresses), and these considerations point to different sizes for different uses.  However, considerations of economy in design strongly push for one size, or a very few sizes related by multiples or fractions (submultiples) to a primary size.  That preferred size becomes the word size of the architecture.

[[Character (computing)|Character]] size was in the past (pre-variable-sized [[character encoding]]) one of the influences on unit of address resolution and the choice of word size.  Before the mid-1960s, characters were most often stored in six bits; this allowed no more than 64 characters, so the alphabet was limited to upper case.  Since it is efficient in time and space to have the word size be a multiple of the character size, word sizes in this period were usually multiples of 6 bits (in binary machines).  A common choice then was the [[36-bit word length|36-bit word]], which is also a good size for the numeric properties of a floating point format.

After the introduction of the [[IBM]] [[System/360]] design, which uses eight-bit characters and supports lower-case letters, the standard size of a character (or more accurately, a [[byte]]) becomes eight bits.  Word sizes thereafter are naturally multiples of eight bits, with 16, 32, and 64 bits being commonly used.
<!-- Maybe this is too much detail as not about word size:
[[Character encoding]]s that handle multiple alphabetic [[writing system]]s, and non-alphabetic writing systems, such as [[Shift JIS]], the [[Extended Unix Code]] (EUC) encodings, [[UTF-8]], and [[UTF-16]], use multiple bytes for some or all characters, decoupling the size of a character from the byte size or word size. -->

=== {{anchor|Variable word length}}Variable-word architectures ===
Early machine designs included some that used what is often termed a ''variable word length''.  In this type of organization, an operand has no fixed length. Depending on the machine and the instruction, the length might be denoted by a count field, by a delimiting character, or by an additional bit called, e.g., flag, or [[word mark (computer hardware)|word mark]].  Such machines often use [[binary-coded decimal]] in 4-bit digits, or in 6-bit characters, for numbers.  This class of machines includes the [[IBM 702]], [[IBM 705]], [[IBM 7080]], [[IBM 7010]], [[UNIVAC 1050]], [[IBM 1401]], [[IBM 1620]], and [[RCA]] 301.

Most of these machines work on one unit of memory at a time and since each instruction or datum is several units long, each instruction takes several cycles just to access memory.  These machines are often quite slow because of this.  For example, instruction fetches on an [[IBM 1620 Model I]] take 8 cycles (160&nbsp;μs) just to read the 12 digits of the instruction (the [[IBM 1620 Model II|Model II]] reduced this to 6 cycles, or 4 cycles if the instruction did not need both address fields). Instruction execution takes a variable number of cycles, depending on the size of the operands.

=== Word, bit and byte addressing ===
{{Main | word addressing | byte addressing }}
The memory model of an architecture is strongly influenced by the word size.  In particular, the resolution of a memory address, that is, the smallest unit that can be designated by an address, has often been chosen to be the word.  In this approach, the [[word-addressable]] machine approach, address values which differ by one designate adjacent memory words.  This is natural in machines which deal almost always in word (or multiple-word) units, and has the advantage of allowing instructions to use minimally sized fields to contain addresses, which can permit a smaller instruction size or a larger variety of instructions.

When byte processing is to be a significant part of the workload, it is usually more advantageous to use the [[byte]], rather than the word, as the unit of address resolution. Address values which differ by one designate adjacent bytes in memory.  This allows an arbitrary character within a character string to be addressed straightforwardly.  A word can still be addressed, but the address to be used requires a few more bits than the word-resolution alternative.  The word size needs to be an integer multiple of the character size in this organization.  This addressing approach was used in the IBM 360, and has been the most common approach in machines designed since then.

When the workload involves processing fields of different sizes, it can be advantageous to address to the bit. Machines with bit addressing may have some instructions that use a programmer-defined byte size and other instructions that operate on fixed data sizes. As an example, on the [[IBM 7030]]<ref>{{Cite manual
 | title       = Reference Manual 7030 Data Processing System
 | date        = August 1961
 |     section = Format
 | section-url = http://bitsavers.org/pdf/ibm/7030/22-6530-2_7030RefMan.pdf#page=59
 |       pages = 50–57
 | url         = http://bitsavers.org/pdf/ibm/7030/22-6530-2_7030RefMan.pdf
 | access-date = December 15, 2021
 | publisher   = IBM
 }}
</ref> ("Stretch"), a floating point instruction can only address words while an integer arithmetic instruction can specify a field length of 1-64 bits, a byte size of 1-8 bits and an accumulator offset of 0-127 bits. 

In a [[byte-addressable]] machine with storage-to-storage (SS) instructions, there are typically move instructions to copy one or multiple bytes from one arbitrary location to another. In a byte-oriented ([[byte-addressable]]) machine without SS instructions, moving a single byte from one arbitrary location to another is typically:
# LOAD the source byte
# STORE the result back in the target byte

Individual bytes can be accessed on a word-oriented machine in one of two ways.  Bytes can be manipulated by a combination of shift and mask operations in registers. Moving a single byte from one arbitrary location to another may require the equivalent of the following:
# LOAD the word containing the source byte
# [[Bitwise operation#Bit_shifts|SHIFT]] the source word to align the desired byte to the correct position in the target word
# [[Bitwise operation#AND|AND]] the source word with a mask to zero out all but the desired bits
# LOAD the word containing the target byte
# AND the target word with a mask to zero out the target byte
# [[Bitwise operation#OR|OR]] the registers containing the source and target words to insert the source byte
# STORE the result back in the target location

Alternatively many word-oriented machines implement byte operations with instructions using special ''byte pointers'' in registers or memory.  For example, the [[PDP-10]] byte pointer contained the size of the byte in bits (allowing different-sized bytes to be accessed), the bit position of the byte within the word, and the word address of the data.  Instructions could automatically adjust the pointer to the next byte on, for example, load and deposit (store) operations.

=== Powers of two ===
Different amounts of memory are used to store data values with different degrees of precision. The commonly used sizes are usually a [[power of two]] multiple of the unit of address resolution (byte or word).  Converting the index of an item in an array into the memory address offset of the item then requires only a [[Arithmetic shift|shift]] operation rather than a multiplication. In some cases this relationship can also avoid the use of division operations. As a result, most modern computer designs have word sizes (and other operand sizes) that are a power of two times the size of a byte.

== Size families ==
As computer designs have grown more complex, the central importance of a single word size to an architecture has decreased.  Although more capable hardware can use a wider variety of sizes of data, market forces exert pressure to maintain [[backward compatibility]] while extending processor capability.  As a result, what might have been the central word size in a fresh design has to coexist as an alternative size to the original word size in a backward compatible design. The original word size remains available in future designs, forming the basis of a size family.

In the mid-1970s, [[Digital Equipment Corporation|DEC]] designed the [[VAX]] to be a 32-bit successor of the 16-bit [[PDP-11]]. They used ''word'' for a 16-bit quantity, while ''longword'' referred to a 32-bit quantity; this terminology is the same as the terminology used for the PDP-11. This was in contrast to earlier machines, where the natural unit of addressing memory would be called a ''word'', while a quantity that is one half a word would be called a ''halfword''. In fitting with this scheme, a VAX ''quadword'' is 64 bits.  They continued this 16-bit word/32-bit longword/64-bit quadword terminology with the 64-bit [[DEC Alpha|Alpha]].

Another example is the [[x86]] family, of which processors of three different word lengths (16-bit, later 32- and 64-bit) have been released, while ''word'' continues to designate a 16-bit quantity. As software is routinely [[Porting|ported]] from one word-length to the next, some [[Application Programming Interface|APIs]] and documentation define or refer to an older (and thus shorter) word-length than the full word length on the CPU that software may be compiled for. Also, similar to how bytes are used for small numbers in many programs, a shorter word (16 or 32 bits) may be used in contexts where the range of a wider word is not needed (especially where this can save considerable stack space or cache memory space). For example, Microsoft's [[Windows API]] maintains the [[programming language]] definition of ''WORD'' as 16 bits, despite the fact that the API may be used on a 32- or 64-bit x86 processor, where the standard word size would be 32 or 64 bits, respectively. Data structures containing such different sized words refer to them as:
* ''WORD'' (16 bits/2 bytes)
* ''DWORD'' (32 bits/4 bytes)
* ''QWORD'' (64 bits/8 bytes)
A similar phenomenon has developed in [[Intel|Intel's]] x86 [[assembly language]] – because of the support for various sizes (and backward compatibility) in the instruction set, some instruction mnemonics carry "d" or "q" identifiers denoting "double-", "quad-" or "double-quad-", which are in terms of the architecture's original 16-bit word size.

An example with a different word size is the [[IBM]] [[System/360]] family. In the [[System/360 architecture]], [[System/370 architecture]] and [[System/390]] architecture, there are 8-bit ''byte''s, 16-bit ''halfword''s, 32-bit ''word''s and 64-bit ''doubleword''s. The [[z/Architecture]], which is the 64-bit member of that architecture family, continues to refer to 16-bit ''halfword''s, 32-bit ''word''s, and 64-bit ''doubleword''s, and additionally features 128-bit ''quadword''s.

In general, new processors must use the same data word lengths and virtual address widths as an older processor to have [[binary-code compatibility|binary compatibility]] with that older processor.

Often carefully written source code &ndash; written with [[source-code compatibility]] and [[software portability]] in mind &ndash; can be recompiled to run on a variety of processors, even ones with different data word lengths or different address widths or both.

== Table of word sizes ==
{{sort-under}}
{| class="wikitable sortable sort-under" style="margin:auto;"
|-
!colspan=8|''key:'' bit: [[bit]]s, ''c'': characters, d: [[decimal digit]]s, ''w'': word size of architecture, ''n'': variable size, wm: [[word mark (computer hardware)|word mark]]
|- style="text-align:center;"
! data-sort-type="number" | Year
!                           Computer architecture
! data-sort-type="number" | Word size ''w''
! data-sort-type="number" | Integer sizes
! data-sort-type="number" | Floating point sizes
! data-sort-type="number" | Instruction sizes
!                           Unit of address resolution
! data-sort-type="number" | Char size
|- style="text-align:center;"
|1837
|[[Charles Babbage|Babbage]]<br>[[Analytical engine]]
|{{val|50|u=[[decimal digit|d]]}}
|''w''
| {{sdash}}
|Five different cards were used for different functions, exact size of cards not known.
|''w''
| {{sdash}}
|- style="text-align:center;"
|1941
|[[Z3 (computer)|Zuse Z3]]
|{{val|22|ul=bit}}
| {{sdash}}
|''w''
|{{val|8|u=bit}}
|''w''
| {{sdash}}
|- style="text-align:center;"
|1942
|[[Atanasoff–Berry Computer|ABC]]
|{{val|50|u=bit}}
|''w''
| {{sdash}}
| {{sdash}}
| {{sdash}}
| {{sdash}}
|- style="text-align:center;"
|1944
|[[Harvard Mark I]]
|{{val|23|u=d}}
|''w''
| {{sdash}}
|{{val|24|u=bit}}
| {{sdash}}
| {{sdash}}
|- style="text-align:center;"
|1946<br />(1948)<br />{1953}
|[[ENIAC]]<br />(w/Panel #16<ref name="Eniac_coding"/>)<br />{w/Panel #26<ref name="Eniac_coding_8"/>}
|{{val|10|u=d}}
|''w'', 2''w''<br />(w)<br />{w}
| {{sdash}}
| {{sdash}}<br />({{val|2|u=d}}, {{val|4|u=d}}, {{val|6|u=d}}, {{val|8|u=d}})<br />{{mset|{{val|2|u=d}}, {{val|4|u=d}}, {{val|6|u=d}}, {{val|8|u=d}}}}
| —<br />—<br />{w}
| {{sdash}}
|- style="text-align:center;"
|1948
|[[Manchester Baby]]
|{{val|32|u=bit}}
|''w''
| {{sdash}}
|''w''
|''w''
| {{sdash}}
|- style="text-align:center;"
|1951
|[[UNIVAC I]]
|{{val|12|u=d}}
|''w''
| {{sdash}}
|{{1/2}}''w''
|''w''
|{{val|1|u=d}}
|- style="text-align:center;"
|1952
|[[IAS machine]]
|{{val|40|u=bit}}
|''w''
| {{sdash}}
|{{1/2}}''w''
|''w''
|{{val|5|u=bit}}
|- style="text-align:center;"
|1952
|[[Fast Universal Digital Computer M-2]]
|{{val|34|u=bit}}
|{{dunno|''w?''}}
|''w''
|{{val|34|u=bit}} = 4-bit opcode plus 3×10&nbsp;bit address
|{{val|10|u=bit}}
| {{sdash}}
|- style="text-align:center;"
|1952
|[[IBM 701]]
|{{val|36|u=bit}}
|{{1/2}}''w'', ''w''
| {{sdash}}
|{{1/2}}''w''
|{{1/2}}''w'', ''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1952
|[[UNIVAC 60]]
|''n'' d
|{{val|1|u=d}}, ... {{val|10|u=d}}
| {{sdash}}
| {{sdash}}
| {{sdash}}
|{{val|2|u=d}}, {{val|3|u=d}}
|- style="text-align:center;"
|1952
|[[ARRA (computer)|ARRA I]]
|{{val|30|u=bit}}
|''w''
| {{sdash}}
|''w''
|''w''
|{{val|5|u=bit}}
|- style="text-align:center;"
|1953
|[[IBM 702]]
|''n'' c
|0 c, ... 511 c
| {{sdash}}
|5 c
|c
|{{val|6|u=bit}}
|- style="text-align:center;"
|1953
|[[UNIVAC 120]]
|''n'' d
|{{val|1|u=d}}, ... {{val|10|u=d}}
| {{sdash}}
| {{sdash}}
| {{sdash}}
|{{val|2|u=d}}, {{val|3|u=d}}
|- style="text-align:center;"
|1953
|[[ARRA II (computer)|ARRA II]]
|{{val|30|u=bit}}
|''w''
|2''w''
|{{1/2}}''w''
|''w''
|{{val|5|u=bit}}
|- style="text-align:center;"
|1954<br>(1955)
|[[IBM 650]]<br>(w/[[IBM 653]])
|{{val|10|u=d}}
|''w''
| {{sdash}}<br>(w)
|''w''
|''w''
|{{val|2|u=d}}
|- style="text-align:center;"
|1954
|[[IBM 704]]
|{{val|36|u=bit}}
|''w''
|''w''
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1954
|[[IBM 705]]
|''n'' c
|0 c, ... 255 c
| {{sdash}}
|5 c
|c
|{{val|6|u=bit}}
|- style="text-align:center;"
|1954
|[[IBM Naval Ordnance Research Calculator|IBM NORC]]
|{{val|16|u=d}}
|''w''
|''w'', 2''w''
|''w''
|''w''
| {{sdash}}
|- style="text-align:center;"
|1956
|[[IBM 305]]
|''n'' d
|{{val|1|u=d}}, ... {{val|100|u=d}}
| {{sdash}}
|{{val|10|u=d}}
|d
|{{val|1|u=d}}
|- style="text-align:center;"
|1956
|[[ARMAC (computer)|ARMAC]]
|{{val|34|u=bit}}
|''w''
|''w''
|{{1/2}}''w''
|''w''
|{{val|5|u=bit}}, {{val|6|u=bit}}
|- style="text-align:center;"
|1956
|[[LGP-30]]
|{{val|31|u=bit}}
|''w''
| {{sdash}}
|{{val|16|u=bit}}
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1958
|[[UNIVAC II]]
|{{val|12|u=d}}
|''w''
| {{sdash}}
|{{1/2}}''w''
|''w''
|{{val|1|u=d}}
|- style="text-align:center;"
|1958
|[[Semi-Automatic Ground Environment|SAGE]]
|{{val|32|u=bit}}
|{{1/2}}''w''
| {{sdash}}
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1958
|[[Autonetics Recomp II]]
|{{val|40|u=bit}}
|''w'', {{val|79|u=bit}}, {{val|8|u=d}}, {{val|15|u=d}}
|2''w''
|{{1/2}}''w''
|{{1/2}}''w'', ''w''
|{{val|5|u=bit}}
|- style="text-align:center;"
|1958
|[[ZEBRA (computer)|ZEBRA]]
|{{val|33|u=bit}}
|''w'', {{val|65|u=bit}}
|2w
|w
|w
|{{val|5|u=bit}}
|- style="text-align:center;"
|1958
|[[Setun]]
| {{val|6|u=[[trit (computing)|trit]]}} (~{{val|9.5|u=bits}}){{efn|The bit equivalent is computed by taking the amount of [[Entropy_(information_theory)|information entropy]] provided by the trit, which is <math>\log_2(3)</math>. This gives an equivalent of about 9.{{val|51|u=bit}}s for 6 trits.}}
| up to {{val|6|ul=tryte}}
|
| up to {{val|3|u=trytes}}
|
| {{dunno|{{val|4|u=trit}}<sup>?</sup>}}
|- style="text-align:center;"
|1958
|[[Electrologica X1]]
|{{val|27|u=bit}}
|''w''
|2''w''
|''w''
|''w''
|{{val|5|u=bit}}, {{val|6|u=bit}}
|- style="text-align:center;"
|1959
|[[IBM 1401]]
|''n'' c
|1 c, ...
| {{sdash}}
|1 c, 2 c, 4 c, 5 c, 7 c, 8 c
|c
|{{val|6|u=bit}} + wm
|- style="text-align:center;"
|1959<br>(TBD)
|[[IBM 1620]]
|''n'' d
|{{val|2|u=d}}, ...
| {{sdash}}<br>({{val|4|u=d}}, ... {{val|102|u=d}})
|{{val|12|u=d}}
|d
|{{val|2|u=d}}
|- style="text-align:center;"
|1960
|[[UNIVAC LARC|LARC]]
|{{val|12|u=d}}
|''w'', 2''w''
|''w'', 2''w''
|''w''
|''w''
|{{val|2|u=d}}
|- style="text-align:center;"
|1960
|[[CDC 1604]]
|{{val|48|u=bit}}
|''w''
|''w''
|{{1/2}}''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1960
|[[IBM 1410]]
|''n'' c
|1 c, ...
| {{sdash}}
|1 c, 2 c, 6 c, 7 c, 11 c, 12 c
|c
|{{val|6|u=bit}} + wm
|- style="text-align:center;"
|1960
|[[IBM 7070]]
|{{val|10|u=d}}{{efn|Three-state sign}}
|''w'', 1-{{val|9|u=d}}
|''w''
|''w''
|''w'', d
|{{val|2|u=d}}
|- style="text-align:center;"
|1960
|[[PDP-1]]
|{{val|18|u=bit}}
|''w''
| {{sdash}}
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1960
|[[Elliott 803]]
|{{val|39|u=bit}}
|
|
|
|
|
|- style="text-align:center;"
|1961
|[[IBM 7030 Stretch|IBM 7030]]<br>(Stretch)
|{{val|64|u=bit}}
|{{val|1|u=bit}}, ... {{val|64|u=bit}},<br>{{val|1|u=d}}, ... {{val|16|u=d}}
|''w''
|{{1/2}}''w'', ''w''
|bit (integer),<br>{{1/2}}''w'' (branch),<br> ''w'' (float)
|{{val|1|u=bit}}, ... {{val|8|u=bit}}
|- style="text-align:center;"
|1961
|[[IBM 7080]]
|''n'' c
|0 c, ... 255 c
| {{sdash}}
|5 c
|c
|{{val|6|u=bit}}
|- style="text-align:center;"
|1962
|[[GE-600 series|GE-6xx]]
|{{val|36|u=bit}}
|''w'', 2 ''w''
|''w'', 2 ''w'', {{val|80|u=bit}}
|''w''
|''w''
|{{val|6|u=bit}}, {{val|9|u=bit}}
|- style="text-align:center;"
|1962
|[[UNIVAC III]]
|{{val|25|u=bit}}
|''w'', 2''w'', 3''w'', 4''w'', {{val|6|u=d}}, {{val|12|u=d}}
| {{sdash}}
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1962
|Autonetics [[D-17B]]<br>[[Minuteman I]] Guidance Computer
|{{val|27|u=bit}}
|{{val|11|u=bit}}, {{val|24|u=bit}}
| {{sdash}}
|{{val|24|u=bit}}
|''w''
| {{sdash}}
|- style="text-align:center;"
|1962
|[[UNIVAC 1107]]
|{{val|36|u=bit}}
|{{frac|1|6}}''w'', {{frac|1|3}}''w'', {{1/2}}''w'', ''w''
|''w''
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1962
|[[IBM 7010]]
|''n'' c
|1 c, ...
| {{sdash}}
|1 c, 2 c, 6 c, 7 c, 11 c, 12 c
|c
|6 b + wm
|- style="text-align:center;"
|1962
|[[IBM 7094]]
|{{val|36|u=bit}}
|''w''
|''w'', 2''w''
|''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1962
|[[SDS 9 Series]]
|{{val|24|u=bit}}
|''w''
|2''w''
|''w''
|''w''
|
|- style="text-align:center;"
|1963<br>(1966)
|[[Apollo Guidance Computer]]
|{{val|15|u=bit}}
|''w''
| {{sdash}}
|''w'', 2''w''
|''w''
| {{sdash}}
|- style="text-align:center;"
|1963
|[[Saturn Launch Vehicle Digital Computer]]
|{{val|26|u=bit}}
|''w''
| {{sdash}}
|{{val|13|u=bit}}
|''w''
| {{sdash}}
|- style="text-align:center;"
|1964/<br>1966
|[[PDP-6]]/[[PDP-10]]
|{{val|36|u=bit}}
|''w''
|''w'', 2 ''w''
|''w''
|''w''
|{{val|6|u=bit}}<br>{{val|7|u=bit}} (typical)<br>{{val|9|u=bit}}
|- style="text-align:center;"
|1964
|[[Titan (1963 computer) | Titan ]]
|{{val|48|u=bit}}
|''w''
|''w''
|''w''
|''w''
|''w''
|- style="text-align:center;"
|1964
|[[CDC 6600]]
|{{val|60|u=bit}}
|''w''
|''w''
|{{1/4}}''w'', {{1/2}}''w''
|''w''
|{{val|6|u=bit}}
|- style="text-align:center;"
|1964
|Autonetics [[D-37C]]<br>[[Minuteman II]] Guidance Computer
|{{val|27|u=bit}}
|{{val|11|u=bit}}, {{val|24|u=bit}}
| {{sdash}}
|{{val|24|u=bit}}
|''w''
|{{val|4|u=bit}}, {{val|5|u=bit}}
|- id="IBM360Row" style="text-align:center;"
|1965
|[[Gemini Guidance Computer]]
|{{val|39|u=bit}}
|{{val|26|u=bit}}
| {{sdash}}
|{{val|13|u=bit}}
|{{val|13|u=bit}}, 26 
| {{sdash}}bit
|- style="text-align:center;"
|1965
|[[IBM 1130]]
|{{val|16|u=bit}}
|''w'', ''2w''
|''2w'', ''3w''
|''w'', ''2w''
|''w''
| {{val|8|u=bit}}
|- style="text-align:center;"
|1965
|[[IBM System/360]]
|{{val|32|u=bit}}
|{{1/2}}''w'', ''w'',<br>{{val|1|u=d}}, ... {{val|16|u=d}}
|''w'', 2''w''
|{{1/2}}''w'', ''w'', 1{{1/2}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1965
|[[UNIVAC 1108]]
|{{val|36|u=bit}}
|{{frac|1|6}}''w'', {{1/4}}''w'', {{frac|1|3}}''w'', {{1/2}}''w'', ''w'', 2''w''
|''w'', 2''w''
|''w''
|''w''
|{{val|6|u=bit}}, {{val|9|u=bit}}
|- style="text-align:center;"
|1965
|[[PDP-8]]
|{{val|12|u=bit}}
|''w''
| {{sdash}}
|''w''
|''w''
|{{val|8|u=bit}} <!-- Used ASR-33 Teletype ASCII -->
|- style="text-align:center;"
|1965
|[[Electrologica X8]]
|{{val|27|u=bit}}
|''w''
|2''w''
|''w''
|''w''
|{{val|6|u=bit}}, {{val|7|u=bit}}
|- style="text-align:center;"
|1966
|[[SDS Sigma series|SDS Sigma 7]]
|{{val|32|u=bit}}
|{{1/2}}''w'', ''w''
|''w'', 2''w''
|''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1969
|[[Four-Phase Systems AL1]]
|{{val|8|u=bit}}
|''w''
| {{sdash}}
|?
|?
|?
|- style="text-align:center;"
|1970
|[[MP944]]
|{{val|20|u=bit}}
|''w''
| {{sdash}}
|?
|?
|?
|- style="text-align:center;"
|1970
|[[PDP-11]]
|{{val|16|u=bit}}
|''w''
|2''w'', 4''w''
|''w'', 2''w'', 3''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1971
|[[CDC STAR-100]]
|{{val|64|u=bit}}
||{{1/2}}''w'', ''w''
||{{1/2}}''w'', ''w''
||{{1/2}}''w'', ''w''
|bit
|{{val|8|u=bit}}
|- style="text-align:center;"
|1971
|[[Texas Instruments TMS1000#History|TMS1802NC]]
|{{val|4|u=bit}}
|''w''
| {{sdash}}
|?
|?
| {{sdash}}
|- style="text-align:center;"
|1971
|[[Intel 4004]]
|{{val|4|u=bit}}
|''w'', d
| {{sdash}}
|2''w'', 4''w''
|''w''
| {{sdash}}
|- style="text-align:center;"
|1972
|[[Intel 8008]]
|{{val|8|u=bit}}
|''w'', {{val|2|u=d}}
| {{sdash}}
|''w'', 2''w'', 3''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1972
|[[Calcomp 900]]
|{{val|9|u=bit}}
|''w''
| {{sdash}}
|''w'', 2''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1974
|[[Intel 8080]]
|{{val|8|u=bit}}
|''w'', 2''w'', {{val|2|u=d}}
| {{sdash}}
|''w'', 2''w'', 3''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1975
|[[ILLIAC IV]]
|{{val|64|u=bit}}
|''w''
|''w'', {{1/2}}''w''
|''w''
|''w''
| {{sdash}}
|- style="text-align:center;"
|1975
|[[Motorola 6800]]
|{{val|8|u=bit}}
|''w'', {{val|2|u=d}}
| {{sdash}}
|''w'', 2''w'', 3''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1975
|[[MOS Technology 6501|MOS Tech. 6501]]<br>[[MOS Technology 6502|MOS Tech. 6502]]
|{{val|8|u=bit}}
|''w'', {{val|2|u=d}}
| {{sdash}}
|''w'', 2''w'', 3''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1976
|[[Cray-1]]
|{{val|64|u=bit}}
|{{val|24|u=bit}}, ''w''
|''w''
|{{1/4}}''w'', {{1/2}}''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1976
|[[Zilog Z80]]
|{{val|8|u=bit}}
|''w'', 2''w'', {{val|2|u=d}}
| {{sdash}}
|''w'', 2''w'', 3''w'', 4''w'', 5''w''
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1978<br>(1980)
|16-bit [[x86]] ([[Intel 8086]])<br>(w/floating point: [[Intel 8087]])
|{{val|16|u=bit}}
|{{1/2}}''w'', ''w'', {{val|2|u=d}}
| {{sdash}}<br>(2''w'', 4''w'', 5''w'', {{val|17|u=d}})
|{{1/2}}''w'', ''w'', ... 7''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1978
|[[VAX]]
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w'', {{val|1|u=d}}, ... {{val|31|u=d}}, {{val|1|u=bit}}, ... {{val|32|u=bit}}
|''w'', 2''w''
|{{1/4}}''w'', ... 14{{1/4}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1979<br>(1984)
|[[Motorola 68000 series]]<br>(w/floating point)
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w'', {{val|2|u=d}}
| {{sdash}}<br>(''w'', 2''w'', 2{{1/2}}''w'')
|{{1/2}}''w'', ''w'', ... 7{{1/2}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1985
|[[IA-32]] ([[Intel 80386]]) (w/floating point)
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w''
| {{sdash}}<br>(''w'', 2''w'', {{val|80|u=bit}})
|{{val|8|u=bit}}, ... {{val|120|u=bit}}<br>{{1/4}}''w'' ... 3{{3/4}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1985
|[[ARM architecture|ARMv1]]
|{{val|32|u=bit}}
|{{1/4}}''w'', ''w''
| {{sdash}}
|''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1985
|[[MIPS architecture#MIPS I|MIPS I]]
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w''
|''w'', 2''w''
|''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1991
|[[Cray C90]]
|{{val|64|u=bit}}
|{{val|32|u=bit}}, ''w''
|''w''
|{{1/4}}''w'', {{1/2}}''w'', {{val|48|u=bit}}
|''w''
|{{val|8|u=bit}}
|- style="text-align:center;"
|1992
|[[DEC Alpha|Alpha]]
|{{val|64|u=bit}}
|{{val|8|u=bit}}, {{1/4}}''w'', {{1/2}}''w'', ''w''
|{{1/2}}''w'', ''w''
|''{{1/2}}w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1992
|[[PowerPC]]
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w''
|''w'', 2''w''
|''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|1996
|[[ARM architecture|ARMv4]]<br/>(w/[[ARM Thumb|Thumb]])
|{{val|32|u=bit}}
|{{1/4}}''w'', {{1/2}}''w'', ''w''
| {{sdash}}
|''w''<br/>({{1/2}}''w'', ''w'')
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|2000
|[[z/Architecture|IBM z/Architecture]]
|{{val|64|u=bit}}{{efn|Although z/Architecture is an inherently 64-bit architecture, the term word still refers to a 32-bit quantity.  However, in this table the sizes are treated as if a word were {{val|64|u=bit}}s.}}
|{{val|8|u=bit}}, {{1/4}}''w'', {{1/2}}''w'', ''w''<br>{{val|1|u=d}}, ... {{val|31|u=d}}
|{{1/2}}''w'', ''w'', 2''w''
|{{1/4}}''w'', {{1/2}}''w'', {{3/4}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}, [[UTF-16]], [[UTF-32]]
|- style="text-align:center;"
|2001
|[[IA-64]]
|{{val|64|u=bit}} 
|{{val|8|u=bit}}, {{1/4}}''w'', {{1/2}}''w'', ''w''
|{{1/2}}''w'', ''w''
|{{val|41|u=bit}} <small>(in 128-bit bundles)</small><ref>{{cite manual
 | title       = Intel Itanium Architecture Software Developer's Manual
 | volume      = 3: Intel Itanium Instruction Set Reference
 | chapter     = 4. Instruction Formats
 | chapter-url = https://www.intel.com/content/dam/www/public/us/en/documents/manuals/itanium-architecture-vol-3-manual.pdf#page=302
 | page        = 3:293
 | quote       = Three instructions are grouped together into 128-bit sized and aligned containers called '''bundles'''. Each bundle contains three 41-bit '''instruction slots''' and a 5-bit template field. 
 | access-date = April 25, 2022
 }}
</ref>
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|2001
|[[ARMv6]]<br/>(w/VFP)
|{{val|32|u=bit}}
|{{val|8|u=bit}}, {{1/2}}''w'', ''w''
| {{sdash}}<br/>(w, 2w)
|{{1/2}}''w'', ''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|2003
|[[x86-64]]
|{{val|64|u=bit}}
|{{val|8|u=bit}}, {{1/4}}''w'', {{1/2}}''w'', ''w''
|{{1/2}}''w'', ''w'', {{val|80|u=bit}}
|{{val|8|u=bit}}, ... {{val|120|u=bit}}
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|- style="text-align:center;"
|2013
|[[ARMv8|ARMv8-A]] and ARMv9-A
|{{val|64|u=bit}}
|{{val|8|u=bit}}, {{1/4}}''w'', {{1/2}}''w'', ''w''
|{{1/2}}''w'', ''w''
|{{1/2}}''w''
|{{val|8|u=bit}}
|{{val|8|u=bit}}
|-
! data-sort-type="number" | Year
!                           Computer architecture
! data-sort-type="number" | Word size ''w''
! data-sort-type="number" | Integer sizes
! data-sort-type="number" | Floating point sizes
! data-sort-type="number" | Instruction sizes
!                           Unit of address resolution
! data-sort-type="number" | Char size
|- style="text-align:center;"
!colspan=8|''key:'' bit: [[bit]]s, ''c'': characters, d: [[decimal digit]]s, ''w'': word size of architecture, ''n'': variable size, wm: [[word mark (computer hardware)|word mark]]
|}<ref name="dd"/><ref name="ddd"/>

== See also ==
* {{Annotated link|Syllable (computing)|Syllable}}

== Notes ==
{{notelist}}

== References ==
{{reflist|refs=
<ref name="Eniac_coding">{{cite web |title=A Logical Coding System Applied to the ENIAC (Electronic Numerical Integrator and Computer) |id=Report No. 673; Project No. TB3-0007 of the Research and Development Division, Ordnance Department |author-first=Richard F. |author-last=Clippinger |author-link=:de:Richard Clippinger |date=1948-09-29 |publisher=[[Ballistic Research Laboratories]] |location=Aberdeen Proving Ground, Maryland, US |url=http://ftp.arl.mil/~mike/comphist/48eniac-coding/ |access-date=2017-04-05 }}</ref>
<ref name="Eniac_coding_8">{{cite web |title=A Logical Coding System Applied to the ENIAC |at=Section VIII: Modified ENIAC |author-first=Richard F. |author-last=Clippinger |author-link=:de:Richard Clippinger |date=1948-09-29 |publisher=[[Ballistic Research Laboratories]] |location=Aberdeen Proving Ground, Maryland, US |url=http://ftp.arl.mil/~mike/comphist/48eniac-coding/sec8.html |access-date=2017-04-05 }}</ref>
<ref name="dd">{{cite book |author-first1=Gerrit Anne |author-last1=Blaauw |author-link1=Gerrit Anne Blaauw |author-first2=Frederick Phillips |author-last2=Brooks, Jr. |author-link2=Frederick Phillips Brooks, Jr. |title=Computer Architecture: Concepts and Evolution |publisher=[[Addison-Wesley]] |date=1997 |edition=1 |isbn=0-201-10557-8}} (1213 pages) (NB. This is a single-volume edition. This work was also available in a two-volume version.)</ref>
<ref name="ddd">{{cite book |author-first1=Anthony |author-last1=Ralston |author-first2=Edwin D. |author-last2=Reilly |title=Encyclopedia of Computer Science |edition=3rd |publisher=[[Van Nostrand Reinhold]] |date=1993 |isbn=0-442-27679-6}}</ref>
<ref name="Buchholz_1962">{{cite book |title=Planning a Computer System – Project Stretch |author-first1=Gerrit Anne |author-last1=Blaauw |author-link1=Gerrit Anne Blaauw |author-first2=Frederick Phillips |author-last2=Brooks, Jr. |author-link2=Frederick Phillips Brooks, Jr. |author-first3=Werner |author-last3=Buchholz |author-link3=Werner Buchholz |editor-first=Werner |editor-last=Buchholz |editor-link=Werner Buchholz |publisher=[[McGraw-Hill Book Company, Inc.]] / The Maple Press Company, York, PA. |lccn=61-10466 |date=1962 |chapter=4: Natural Data Units |pages=39–40 |chapter-url=http://archive.computerhistory.org/resources/text/IBM/Stretch/pdfs/Buchholz_102636426.pdf |access-date=2017-04-03 |url-status=live |archive-url=https://web.archive.org/web/20170403014651/http://archive.computerhistory.org/resources/text/IBM/Stretch/pdfs/Buchholz_102636426.pdf |archive-date=2017-04-03 |quote=[...] Terms used here to describe the structure imposed by the machine design, in addition to ''[[bit]]'', are listed below.<br/>''[[Byte]]'' denotes a group of bits used to encode a character, or the number of bits transmitted in parallel to and from input-output units. A term other than ''[[character (computing)|character]]'' is used here because a given character may be represented in different applications by more than one code, and different codes may use different numbers of bits (i.e., different byte sizes). In input-output transmission the grouping of bits may be completely arbitrary and have no relation to actual characters. (The term is coined from ''[[bite]]'', but respelled to avoid accidental mutation to ''bit''.)<br/>A ''word'' consists of the number of data bits transmitted in parallel from or to memory in one memory cycle. [[Word size]] is thus defined as a structural property of the memory. (The term ''[[catena (unit)|catena]]'' was coined for this purpose by the designers of the [[Groupe Bull|Bull]] {{ill|Bull Gamma 60{{!}}GAMMA 60|fr|Gamma 60}} computer.)<br/>''[[Block (data storage)|Block]]'' refers to the number of words transmitted to or from an input-output unit in response to a single input-output instruction. Block size is a structural property of an input-output unit; it may have been fixed by the design or left to be varied by the program. [...]}}</ref>
<ref name="Dreyfus_1958_Gamma60">{{cite conference |title=System design of the Gamma 60 |author-first=Phillippe |author-last=Dreyfus |author-link=Philippe Dreyfus |conference=[[Western Joint Computer Conference]]: Contrasts in Computers |location=Los Angeles, California, US |date=1958-05-08 |orig-year=1958-05-06 |id=IRE-ACM-AIEE '58 (Western) |publication-place=ACM, New York, NY, US |pages=130–133 |url=https://www.computer.org/csdl/proceedings/afips/1958/5052/00/50520130.pdf |access-date=2017-04-03 |url-status=live |archive-url=https://web.archive.org/web/20170403224547/https://www.computer.org/csdl/proceedings/afips/1958/5052/00/50520130.pdf |archive-date=2017-04-03 |quote=[...] Internal data code is used: Quantitative (numerical) data are coded in a 4-bit decimal code; qualitative (alpha-numerical) data are coded in a 6-bit alphanumerical code. The internal [[instruction code]] means that the instructions are coded in straight binary code.<br/>As to the internal information length, the information quantum is called a "[[catena (unit)|catena]]," and it is composed of 24 bits representing either 6 decimal digits, or 4 alphanumerical characters. This quantum must contain a multiple of 4 and 6 bits to represent a whole number of decimal or alphanumeric characters. Twenty-four bits was found to be a good compromise between the minimum 12 bits, which would lead to a too-low transfer flow from a parallel readout core memory, and 36 bits or more, which was judged as too large an information quantum. The catena is to be considered as the equivalent of a [[character (computing)|character]] in variable word length machines, but it cannot be called so, as it may contain several characters. It is transferred in series to and from the main memory.<br/>Not wanting to call a "quantum" a word, or a set of characters a letter, (a word is a word, and a quantum is something else), a new word was made, and it was called a "catena." It is an English word and exists in [[Webster's]] although it does not in French. Webster's definition of the word catena is, "a connected series;" therefore, a 24-bit information item. The word catena will be used hereafter.<br/>The internal code, therefore, has been defined. Now what are the external data codes? These depend primarily upon the information handling device involved. The {{ill|Bull Gamma 60{{!}}Gamma 60|fr|Gamma 60}} is designed to handle information relevant to any binary coded structure. Thus an 80-column punched card is considered as a 960-bit information item; 12 rows multiplied by 80 columns equals 960 possible punches; is stored as an exact image in 960 magnetic cores of the main memory with 2 card columns occupying one catena. [...]}}</ref>
<ref name="Beebe_2017">{{cite book |author-first=Nelson H. F. |author-last=Beebe |title=The Mathematical-Function Computation Handbook - Programming Using the MathCW Portable Software Library |chapter=Chapter I. Integer arithmetic |date=2017-08-22 |location=Salt Lake City, UT, US |publisher=[[Springer International Publishing AG]] |edition=1 |lccn=2017947446 |isbn=978-3-319-64109-6 |doi=10.1007/978-3-319-64110-2 |page=970|s2cid=30244721 }}</ref>
}}

{{Computer Storage Volumes}}
{{Data types}}
{{CPU technologies}}

[[Category:Data types]]
[[Category:Data unit| ]]
[[Category:Primitive types]]
[[Category:Units of information]]