View source for USB4

{{Short description|Technical standard in computing}}
{{Use dmy dates|date=November 2020|cs1-dates=y}}

{{Infobox connector
| name = USB4
| type = [[USB]]
| logo = [[File:Certified USB4 40Gbps Logo.svg|220px|Deprecated USB4 40&nbsp;Gbps logo]]
| caption = Deprecated USB4 40&nbsp;Gbps logo
| designer = USB Promoter Group
| design_date = {{start date and age|2019|08|29|df=y}}
| manufacturer = 
| production_date = 
| superseded = [[USB 3.2]]
| weight = 
| length = 
| diameter = 
| hotplug = 
| daisy_chain = No
| external = 
| electrical = 
| earth = 
| maximum_voltage = 48&nbsp;V (PD 3.1) <!-- this is also somewhat confusing as Type-C regulates this and it has nothing to do with USB4 directly -->
| maximum_current = 5&nbsp;A (PD)
| audio_signal = [[DisplayPort]]
| video_signal = DisplayPort
| data_signal = USB or PCIe
| data_bit_width = 
| data_bandwidth = 20&nbsp;Gbit/s<br/>40&nbsp;Gbit/s<br/>80&nbsp;Gbit/s<br/>120/40&nbsp;Gbit/s asymmetric
| data_devices = 
| data_style = 
| cable = 
| physical_connector = [[USB-C]]
| num_pins = 24
| pinout_col1_name = 
| pinout_col2_name = 
| pinout_image = 
| pinout_caption = 
}}
[[File:USB4 Type-C Gen3x2 Bi-Directional Cable 40Gbps 8K60Hz 100W PowerDelivery.jpg|USB4 Gen3x2 cable (40&nbsp;Gbps) with 100&nbsp;W Power Delivery|thumb]]
'''Universal Serial Bus 4''' ('''USB4'''), sometimes erroneously referred to as '''USB 4.0''', is the most recent technical specification of the [[USB]] (Universal Serial Bus) [[data communication]] standard. The [[USB Implementers Forum]] originally announced USB4 in 2019.

USB4 enables multiple devices to dynamically share a single high-speed [[data link]]. USB4 defines [[data signaling rate|bit rates]] of 20 Gbit/s, 40 Gbit/s and 80 Gbit/s.<ref name="USB4SPEC20">{{harvnb|USB4 Version 2.0 Specification|2023}}</ref><ref>{{cite web |date=2022-10-18 |title=USB-IF Announces Publication of New USB4 Specification to Enable USB 80Gbps Performance |url=https://www.usb.org/sites/default/files/2022-10/USB-IF%20USB%2080Gbps%20Announcement_FINAL_v2.pdf}}</ref> USB4 is only defined for [[USB-C]] connectors and its Type-C specification<ref>{{harvnb|Type-C Cable and Connector Specification|2023}}</ref> regulates the connector, cables and also power delivery features across all uses of USB-C cables, in part<ref>{{harvnb|Type-C Cable and Connector Specification|at=p216f, sec. 4.6}}</ref> with the [[USB hardware#USB Power Delivery|USB Power Delivery]] specification.<ref name="USB Power Delivery Specification 2023">{{harvnb|USB Power Delivery Specification|2023}}</ref>

The USB4 standard mandates backwards compatibility to [[USB 3.0#USB 3.2|USB 3.x]] and dedicated backward compatibility with [[USB#USB 2.0|USB 2.0]].<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p1, sec. 1.5, p12, sec. 2}}</ref> The dynamic sharing of bandwidth of a USB4 connection is achieved by encapsulating multiple virtual connections ("tunnels") of other protocols, such as USB 3.x, [[DisplayPort]] and [[PCI Express]].

USB4 is based on the [[Thunderbolt (interface)#Thunderbolt 3|Thunderbolt 3]] protocol. However, it is different enough that backwards compatibility to Thunderbolt 3 is optional for many device types.<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p15, sec. 2.1.5}}</ref>

==History==
Prior to USB4, [[Thunderbolt (interface)|Thunderbolt]] provided a way to dynamically share bandwidth between multiple {{abbr|DP|DisplayPort}} and PCIe connections over a single cable. Thunderbolt originally used the [[DisplayPort#Mini DisplayPort connector|mDP]] connector and was only backward compatible to {{abbr|DP|DisplayPort}} connections and did not support power transfer.

The introduction of the [[USB-C|Type-C]] connector in 2014 provided a connector that could support USB data connectivity and power transfer as well as {{abbr|DP|DisplayPort}} connections. It also allowed the static sharing of bandwidth between DP and USB connections over the same cable.

Thunderbolt 3 switched over to using the new Type-C connector and also added backwards compatibility for USB connections and power transfer features.

=== USB4 Version 1.0 ===
USB4 was announced in March 2019 by the USB Promoter Group.<ref>{{cite web |url=https://hothardware.com/news/usb4-40-gbps-royalty-free-intel-thunderbolt-3 |title=USB4 Leverages Thunderbolt 3 Protocol Doubling Speeds To 40Gbps |author-first=Brandon |author-last=Hill |date=2019-03-04 |website=HotHardware |access-date=28 April 2020 |archive-date=23 October 2021 |archive-url=https://web.archive.org/web/20211023152301/https://hothardware.com/news/usb4-40-gbps-royalty-free-intel-thunderbolt-3 |url-status=live}}</ref><ref>{{cite web |url=https://www.gsmarena.com/usb4_announced_with_40gbps_bandwidth_its_based_on_thunderbolt_3-news-35841.php |title=USB4 announced with 40Gbps bandwidth, it's based on Thunderbolt 3 |website=GSMArena.com |access-date=29 April 2020 |archive-date=15 January 2022 |archive-url=https://web.archive.org/web/20220115155541/https://www.gsmarena.com/usb4_announced_with_40gbps_bandwidth_its_based_on_thunderbolt_3-news-35841.php |url-status=live}}</ref> The version 1.0 of the USB4 specification, released 29 August 2019, is titled "Universal Serial Bus 4 (USB4™)". Several news reports before the release of that version sometime use the wrong terminology "USB 4.0" and "USB 4".<ref>{{cite web |url=https://techcrunch.com/2019/03/04/with-usb-4-thunderbolt-and-usb-will-converge/ |title=With USB 4, Thunderbolt and USB will converge |date=4 March 2019 |access-date=1 May 2020 |archive-date=10 September 2022 |archive-url=https://web.archive.org/web/20220910201245/https://techcrunch.com/2019/03/04/with-usb-4-thunderbolt-and-usb-will-converge/ |url-status=live}}</ref><ref>{{cite web |url=https://www.guru3d.com/news-story/usb-4-will-arrive-in-late-2020.html |title=USB 4.0 Will Arrive in Late 2020 |author-first=Hilbert |author-last=Hagedoorn |website=Guru3D |date=13 June 2019 |access-date=30 April 2020 |archive-date=26 October 2021 |archive-url=https://web.archive.org/web/20211026182556/https://www.guru3d.com/news-story/usb-4-will-arrive-in-late-2020.html |url-status=live}}</ref>

In the announcement press release, the USB Promoter Group mentions that USB4 is "based on the Thunderbolt™ protocol specification recently contributed by Intel Corporation".<ref>{{cite web |url=https://usb.org/sites/default/files/2019-03/USB_PG_USB4_DevUpdate_Announcement_FINAL_20190226.pdf |title=USB Promoter Group Announces USB4 Specification |author=USB Promoter Group |date=2019-03-04 |website=usb.org |access-date=2024-12-21 }}</ref>
Goals stated in the USB4 specification are increasing bandwidth, helping to converge the USB-C connector ecosystem, and "minimize end-user confusion". Some of the key areas to achieve this are using a single USB-C connector type, to offer display and data transfer features, while retaining "compatibility with existing and [[Thunderbolt (interface)|Thunderbolt]] products".<ref>{{cite web |url=https://usb.org/document-library/usb4tm-specification |archive-url=https://web.archive.org/web/20210419213328/https://usb.org/document-library/usb4tm-specification |title=USB4 Specification |archive-date=2021-04-19 |at=p1, sec 1.4 Design Goals}}</ref>

Version 1.0 defined 20 Gbit/s and 40 Gbit/s connections, the required support of USB 2.0 and USB 3.x connections at up to 10 Gbit/s with support for tunneling connections according to the PCIe 4.0, USB 3.2 and DP 1.4a specifications. Optional backwards compatibility to Thunderbolt 3 as well as Host-to-Host networking were also defined.
Compared to Thunderbolt 3, USB4 changed the raw bit rates slightly to bring them in line with other USB specifications, where the nominal bit rate matches the raw bit rate. USB4 also added support for USB3 tunnels and use of the USB2 wires for improved backwards compatibility with previous USB standards and to allow for simpler USB4 devices without support for PCIe. USB4 also added support for hub topologies compared to Thunderbolts previous restriction to daisy-chaining topology.

In July 2020 Intel announced Thunderbolt 4 as an implementation of USB4 40 Gbit/s with additional requirements, such as mandatory backwards compatibility to Thunderbolt 3 and requirement for smaller notebooks to support being charged over Thunderbolt 4 ports.<ref>{{cite web |url=https://www.anandtech.com/show/15902/intel-thunderbolt-4-update-controllers-and-tiger-lake-in-2020 |title=Intel Thunderbolt 4 Update: Controllers and Tiger Lake in 2020 |author-first=Ian |author-last=Dr. Cutress |date=2020-07-08 |access-date=2024-12-21 }}</ref> Publications such as Anandtech described Thunderbolt 4 as "superset of TB3 and USB4" and "able to accept TB4, TB3, USB4, and USB 3/2/1 connections".
Intel itself describes Thunderbolt 4 as "delivering increased minimum performance requirements, expanded capabilities and USB4 specification compliance" and as building "on the innovation of Thunderbolt 3".<ref>{{cite web |url=https://www.intel.com/content/www/us/en/newsroom/news/thunderbolt-4-universal-cable-connectivity.html |title=Introducing Thunderbolt 4: Universal Cable Connectivity for Everyone |date=2020-07-08 |access-date=2024-12-21 }}</ref>

=== USB4 Version 2.0 ===
On 18 October 2022 the USB Promoter Group released the USB4 Version 2.0 specification.<ref>{{cite web |date=2022-09-01 |title=USB Promoter Group Announces USB4 Version 2.0 |url=https://www.businesswire.com/news/home/20220901005211/en/USB-Promoter-Group-Announces-USB4%C2%AE-Version-2.0 |access-date=2022-09-02 |website=www.businesswire.com |language=en |archive-date=2 September 2022 |archive-url=https://web.archive.org/web/20220902075428/https://www.businesswire.com/news/home/20220901005211/en/USB-Promoter-Group-Announces-USB4%C2%AE-Version-2.0 |url-status=live}}</ref><ref>{{cite web |title=USB-IF Announces Publication of New USB4 Specification to Enable USB 80Gbps Performance |url=https://usb.org/sites/default/files/2022-10/USB-IF%20USB%2080Gbps%20Announcement_FINAL_v2.pdf |website=USB-IF |publisher=USB Implementers Forum |access-date=19 January 2023 |date=18 October 2022}}</ref>

It added a new transmission speed that allows 80 Gbit/s symmetric connections or asymmetric connections supporting 120 Gbit/s in one direction and 40 Gbit/s in the other. The new PAM3 encoding scheme enables this over existing, passive "USB 40Gbps" cables. Active cables are not forwards compatible in the same way, instead a new speed grade of active cables was added.
It also upgraded the support of DP tunnels to DP 2.1, allowing the tunneling of DP connections with up to 80 Gbit/s (UHBR20). It also added a replacement of the previous tunneling of classic USB 3.2 connection speeds with "USB3 Gen T tunneling", which can exceed 20 Gbit/s and also removed PCIe overhead limitations.

Around the release of the new USB4 2.0 specification, USB-IF also mandated new logos and marketing names to simplify representing the maximum supported bit rates and wattages to consumers.<ref>{{Cite web |last=Porter |first=Jon |date=2022-09-30 |title=USB kills off SuperSpeed branding as it tries to simplify its ubiquitous connector |url=https://www.theverge.com/2022/9/30/23378231/usb-rebranding-2022-logos-gbps-wattage-charging-transfer-speeds-simplification-usb4-superspeed |access-date=2024-08-05 |website=The Verge |language=en}}</ref>

In September 2023, Intel announced the launch of Thunderbolt 5 as an implementation of USB4, using the new abilities of 80 Gbit/s connections and updated DP support<ref>{{cite web |url=https://www.anandtech.com/show/20050/intel-unveils-barlow-ridge-thunderbolt-5-controllers |title=Intel Unveils Barlow Ridge Thunderbolt 5 Controllers - TB5 Launching In 2024 |author-first=T S |author-last=Ganesh |date=2023-10-12 |access-date=2024-12-21 }}</ref> Intel's own press release describes it as "built on industry standards – including USB4 V2".<ref>{{cite web |url=https://www.intel.com/content/www/us/en/newsroom/news/intel-introduces-thunderbolt-5-standard.html |title=Intel Introduces Thunderbolt 5 Connectivity Standard |date=2022-10-12 |access-date=2024-12-21 }}</ref>

== Functionality of USB4 ports ==
{{technical | section|date=November 2024}}

Similarly to how [[USB 3.0|USB 3.x]] specifications defined the new SuperSpeed(Plus) protocols for faster signaling rates, they also mandated that USB 3.x physically and architecturally implement USB 2.0 specification with dedicated wires, where the USB4 specification describes 2 different aspects. The first one is what type of existing connections and compatibility a USB4 port guarantees. The USB4 specification speaks of downstream facing ports (DFP) and upstream facing ports (UFP) rather than host and peripheral ports. Downstream facing ports includes host ports as well as any "outputs" of a USB4 hub, while upstream facing ports include anything that is connectable to a downstream facing port, like the ports of peripherals or the "input" port of a USB4 hub.<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p13ff, fig. 2-1 USB4/USB3.2 Dual Bus System Architecture}}</ref>

Any USB4 {{Abbr|DFP|Downstream Facing Port}} port is required to also implement USB 2.0, USB 3.2 and DP Alternative Mode support, each according to their own specifications. As such, a USB4 {{Abbr|DFP|Downstream Facing Port}} is backwards compatible to all previous USB standards and DP output.<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p12ff, sec. 2 Architectural Overview}}</ref>

=== USB 2.0 DFP features ===
[[USB#USB 2.0|USB 2.0]] defines 3 different bit rates (Low-, Full-, High-Speed), all are required to be supported.<ref>{{harvnb|USB 2.0 Specification|2024}}</ref> USB 2.0 abilities uses separate wires on the Type-C connector that are not used by USB 3.2 or USB4.

=== USB 3.x DFP features ===
[[USB 3.0|USB 3.2]], the current version, defines 3 different bit rates ("5 Gbps" a.k.a. SuperSpeed, "10 Gbps" a.k.a. SuperSpeed+, "20 Gbps" a.k.a. SuperSpeed+ 20 Gbps). While USB 3.2 specification<ref>{{harvnb|USB 3.2 Specification|2022}}</ref> has been referenced USB4 from the start, only the 2 lower speeds (5 Gbit/s, 10 Gbit/s) are mandatory for USB4 DFPs to support.

=== DP Alt Mode DFP features ===
The USB4 specifications make no reference to a minimum feature set for its [[DisplayPort#USB-C|DP Alternative Mode]] functionality, but Thunderbolt 3 does. In practice, Intel's family of TB 3 controllers requires at least [[DisplayPort#1.2|DisplayPort 1.2]] at HBR2 speeds to support 4K60 output, but is also available with up to HBR3 speeds according to the [[DisplayPort#1.4a|DisplayPort 1.4a specification]].<ref>{{Cite web |title=Intel® JHL8540 Thunderbolt™ 4 Controller Product Specifications |url=https://www.intel.com/content/www/us/en/products/sku/193684/intel-jhl8540-thunderbolt-4-controller.html |access-date=2024-08-06 |website=www.intel.com |language=en}}</ref>

=== Power transfer features for DFP ===
The USB4 specification makes no explicit demands on power output. It outsources all requirements in terms of power to the Type-C<ref>{{harvnb|Type-C Cable and Connector Specification|2023|at=p244 sec. 5.3}}</ref> specification that underpins all USB, DP and other standards that use the USB-C connector. This requires a USB4 {{Abbr|DFP|Downstream Facing Port}} to supply at least 7.5W Type-C current. No power consumption features (e.g., charging of a notebook) are required, but can be supported following the USB PD specification,<ref name="USB Power Delivery Specification 2023"/> as well as supplying considerably more power. The USB PD protocol must always have support for exchanging data according to the protocol. This is separate from any functionality of PD to negotiate actual power delivery other than 5V or >15W.

=== USB4 hubs & docks ===
USB4 hubs and docks are defined as their own category of USB4 devices that include further requirements. For example, a USB4 hub must also serve as a classic USB 3.2 hub with DP Alternative Mode passthrough with hosts that do not support USB4 connections. See [[#USB4 capabilities by device type|USB4 capabilities by device type]] for more details.

== USB4 protocol/connections ==
Every USB4 port must support the USB4 protocol/connections, which is a distinct standard to establish USB4 links/connections between USB4 devices that exists in parallel to previous USB protocols. Unlike USB 2.0 and USB 3.x, it does not provide a way to transfer data directly, it is rather a mere container that can contain multiple virtual connections ("tunnels").

Other specifications are referenced to define the contents and internal functionality of a tunnel. USB4 defines the following tunnel types:

* USB3 connections
* DisplayPort connections
* PCIe connections
* Ethernet/network connections according to the included USB4Net and Cross-Domain specifications<ref>{{Harvnb|USB4 Version 2.0 Specification Inter-Domain Service|2023}}</ref>

=== General principles of USB4 ===
USB4 forms a tree-like topology of USB4 routers, where each USB4 device includes a USB4 router to participate in this network. A tunnel can be end-to-end, where the route through the entire network of routers is preconfigured. But tunnels can also be single-hop, where it exists only for a single USB4 link (i.e., between 2 routers). In this case, the tunnel will be "unpacked" by the recipient and will use some other means specific to the tunnel type to identify where data needs to be sent next. If the next [[Hop (networking)|hop]] is another USB4 router, data will be ingested again into the next single-hop tunnel until it exits the USB4 network.<ref>{{Harvnb|USB4 Version 2.0 Specification|2023|at=p13}}</ref>

Accordingly, single-hop tunnels require specific support in each USB4 router, just to support passing them through to further USB4 routers. However, end-to-end tunnels require support of a USB4 router only when the data is ingested into the tunnel and at the target, to the point where the tunnel ends.

==== Protocol input/output adapters ====
A Protocol Input Adapter will ingest a connection according to whatever protocol it is based on and convert the contents into a USB4 tunnel. Protocol Output Adapters do the reverse. They extract a tunnel from the USB4 network and if needed recreate a regular connection from the tunnel contents.

The conversion into a tunnel typically entails removing any [[Physical layer|Phy/Electrical]] layer and encoding of the underlying connection standard and potentially losslessly compresses the contents; for example, by leaving out empty filler data. A USB4 tunnel itself is virtual and doesn't need to conform to any fixed bandwidth or other limitations that stem from the Phy/Electrical layer of the underlying connection standard. But since most tunnel types will eventually be converted back to a regular, physical connection again, most of those physical limitations, like max. bandwidth, are still likely to apply in the end.

=== USB3 Gen X tunneling ===
This is a single-hop tunnel that essentially can transport any [[USB 3.0#USB 3.2|Enhanced SuperSpeed connection]] according to the USB 3.2 specification. USB3 Gen X follows the Enhanced SuperSpeed Hub topology, where every USB4 router with more than one USB3 endpoint must include a USB3 hub as well. It is the default way USB3 connections through USB4 are made. Supporting it at 10 Gbit/s (SuperSpeed USB 10 Gbps, Gen 2x1) is mandatory on every USB4 {{Abbr|DFP|Downward Facing Port}}. The minimum supported speed for the USB3 connection being tunneled is 10 Gbit/s as every USB4 device already has to support this speed and USB3 hubs handle converting this to 5 Gbit/s devices that may be connected.

This means, that a USB4 hub will share a single upstream USB3 connection and distribute its bandwidth across all its downstream facing ports that make use of USB3 connections.

=== USB3 Gen T tunneling ===
This is an optional alternative to USB3 Gen X tunneling that was introduced in USB4 Version 2.0. It is an end-to-end variant of USB3 Gen X tunnel.

Through this, it eschews the need for USB3 hubs in every USB4 router that can and will limit the throughput. It allows multiple separate USB3 Gen T tunnels even over shared links. Since it is an end-to-end tunnel, every USB4 hub will support passing it through. USB3 Gen T is intended as exclusively virtual, there exists no physical equivalent for it. Thus, it can only be used inside of a USB4 controller. This allows it to leave the limitations to 10 or 20 Gbit/s connections of USB&nbsp;3.2 behind, while reusing most of the other parts of the [[USB 3.0#USB 3.2|Enhanced SuperSpeed protocol]].<ref>{{Harvnb|USB4 Version 2.0 Specification|2023|at=p487}}</ref>

No known USB4 controller implements support for Gen T tunneling to date (August 2024).

=== DP tunneling ===
DisplayPort is also tunneled as end-to-end connection. There can be multiple independent DP tunnels, but each will be delivered to a single protocol output adapter (at which point [[DisplayPort#Multi-Stream Transport (MST)|DisplayPort MST]] might be used to further split each connection up).

USB4 Version 1.0 only defines how to tunnel DP connections according to the [[DisplayPort#1.4a|DisplayPort 1.4a specification]] (up to HBR3 speeds). USB4 Version 2.0 updates this support to the full [[DisplayPort#2.1|DisplayPort 2.1 specification]] (up to UHBR20 speeds). Notably, the USB4 specification explicitly carves out needing to support the UHBR13.5 DP speed, even if UHBR20 is supported. The DP specification is not public. It is unknown if it makes similar carve-outs.

DP tunneling has great understanding of the contents of DP connections, and will efficiently skip/transmit any filler data, reducing the actually utilized bandwidth of a DP tunnel. But since DP connections have [[Real-time computing|real-time requirements]], bandwidth must be reserved for them. USB4 mandates that in absence of any other information, the maximum possible bandwidth for the particular DP connection (DP lanes and speed) must be reserved. This reservation only applies to other real-time tunnels though. Reserved, but unused bandwidth can be used by non-real-time tunnels such as PCIe or USB3, but the reservation may still block other DP tunnels from being established.<ref>{{Harvnb|USB4 Version 2.0 Specification Connection Manager Guide|2023|at=p59, sec. 6.1}}</ref>

=== PCIe tunneling ===
Similar to USB3 Gen X tunneling, PCIe tunneling uses single-hop tunnels, requiring PCIe switches in every USB4 router that supports PCIe tunneling. USB4 has, from the start, referenced the [[PCI Express#PCI Express 4.0|PCI Express Specification Revision 4]] and with USB4 Version 2.0 added references to [[PCI Express#PCI Express 5.0|PCI Express Specification Revision 5.0]].

PCIe tunneling has had a significant limitation in USB4 Version 1.0 and also Thunderbolt 3: PCIe Express has a [[PCI Express#Transaction Layer|variable maximum payload size]], which applies end-to-end to a transmission. If any one component or PCIe Switch has a limited {{abbr|MPS|Maximum Payload Size}}, all packets passing through must be limited accordingly. Because USB4 uses a payload of up to 256 Byte per USB4 packet and a PCIe tunnel packet contains further PCIe headers and meta data, the MPS for PCIe tunnels was limited to 128 Byte. This limitation can reduce the efficiency of the PCIe connection greatly for all devices and systems that would otherwise support 256 Byte or even larger MPS.

USB4 Version 2.0 removes this bottleneck (mandatory for all implementers), by defining how a larger PCIe packet can be split across multiple USB4 packets. Support for this new feature requires every USB4 component / controller involved in the PCIe tunnel to implement USB4 Version 2.0.<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p660, sec. 11.1.1.1.3}}</ref>

== USB4 signaling modes ==

Signaling refers to the lowest layer of the [[OSI Model#Layer 1: Physical layer|OSI Model]], also called physical layer or phy.
USB4 connections can be expressed with consumer facing names that are also the basis for the official logos used on packaging and products. These are the "20 Gbps", "40 Gbps", "80 Gbps" labels and they do not explicitly indicate how the connection is achieved on the physical layer.
There are also more technical names based on the implementation and use of the USB-C cables. These usually consist of a speed per wire-pair expressed as Gen 1/2/3/4 (5 Gbit/s, 10 Gbit/s, 20 Gbit/s, 40 Gbit/s respectively) and some further information on how many wire-pairs are used in which combination.

USB commonly defines a "Lane" as a (bidirectional) connection, which for all recent transmission modes consists of one sending and one receiving wire-pair. The "Gen AxB" notation refers to B Lanes of operation mode A.
Since Gen 4 modes also introduced asymmetric connections with uneven numbers of wire-pairs dedicated to sending and receiving, the Lane-notation is no longer applicable.

The USB&nbsp;3.x family has had the same technical notation retroactively added in the USB 3.1 and USB 3.2 specification versions. Though this shows common principles and the same generations refer to the same nominal speeds, "Gen A" does not have the same exact meaning in both USB&nbsp;3.x and USB4 specifications. The overlap in naming mainly becomes relevant for cables as shown in [[#Cable compatibility|Cable Compatibility]], which is regulated by the Type-C specification shared across all users of Type-C connector.
{| class="wikitable sortable mw-datatable" style="text-align:center;"
|+ Comparison of signaling modes
! rowspan="2" {{verth|USB family}}
! rowspan="2" | Signaling mode name{{efn|name=usbnaming}}
! rowspan="2" | Introduced in
! rowspan="2" | [[Line code|Encoding]]
! rowspan="2" | Wire-pairs sending/receiving
! colspan="2" | Raw bit rate<br />({{Abbr|Gbit/s|Gigabits per second}})
! rowspan="2" | Net data rate{{efn|name=netdatarate}}<br />({{Abbr|Gbit/s|Gigabits per second}})
! rowspan="2" | [[USB Implementers Forum|USB-IF]]<br />current marketing name<ref name="trademarkReq">[https://usb.org/sites/default/files/trademark_license_agreement_licensed_mark_requirements_final_as_of_september_20_2023.pdf USB Trademark Requirements Chart from USB-IF]</ref>
! rowspan="2" | Logo<ref name="trademarkReq" />
|-
! per wire-pair
! total  (per direction)
|-
| {{verth|USB 2.x}}
| style="white-space: nowrap;"| High-Speed
| USB 2.0
| [[Non-return-to-zero, inverted|NRZI]] with [[bit stuffing]]
| 1 (shared)
| 0.480 (half-duplex)
| 0.480 (half-duplex)
| {{dunno}}<!-- IT IS NOT 0.480. There is encoding overhead. At least for the bit-stuffing -->
| Hi-Speed USB
| [[File:Certified Hi-Speed USB.svg|50px]]
|-
| rowspan="4" {{verth|USB 3.x}}
| style="white-space: nowrap;"| Gen 1x1
| USB 3.0
| [[8b/10b encoding|8b/10b]]
| 1/1
| 5
| 5
| 4
| USB 5Gbps
| [[File:USB 5Gbps logo.svg|50px]]
|-
| style="white-space: nowrap;"| Gen 2x1{{efn|name=diff10&nbsp;gbps}}
| USB 3.1
| [[64b/66b encoding|128b/132b]]
| 1/1
| 10
| 10
| ~9.7
| USB 10Gbps
| [[File:USB 10Gbps logo.svg|50px]]
|-
| style="white-space: nowrap;"| Gen 1x2
| rowspan="2" | USB 3.2
| [[8b/10b encoding|8b/10b]]
| 2/2
| 5
| 10
| 8
| colspan="2" {{n/a|(fallback)}}{{efn|name=usb3gen1x2}}
|-
| style="white-space: nowrap;"| Gen 2x2{{efn|name=diff10&nbsp;gbps}}
| [[64b/66b encoding|128b/132b]]
| 2/2
| 10
| 20
| ~19.39
| USB 20Gbps
| [[File:USB 20Gbps logo.svg|50px]]
|-
| rowspan="7" {{verth|USB4}}
| style="white-space: nowrap;"| Gen 2x1{{efn|name=diff10&nbsp;gbps}}
| rowspan="4" | USB4 v1.0
| rowspan="2" | 64b/66b{{efn|name=rs-fec}}
| 1/1
| 10
| 10
| ~9.697
| colspan=2 {{n/a|(transient/fallback)}}{{efn|name=usb4single}}
|-
| style="white-space: nowrap;"| Gen 2x2{{efn|name=diff10&nbsp;gbps}}
| 2/2
| 10
| 20
| ~19.39
| USB 20Gbps
| [[File:USB 20Gbps logo.svg|50px]]
|-
| style="white-space: nowrap;"| Gen 3x1
| rowspan="2" | 128b/132b{{efn|name=rs-fec}}
| 1/1
| 20
| 20
| ~19.39
| colspan=2 {{n/a|(transient/fallback)}}{{efn|name=usb4single}}
|-
| style="white-space: nowrap;"| Gen 3x2
| 2/2
| 20
| 40
| ~38.79
| USB 40Gbps
| [[File:USB 40Gbps logo 01.svg|50px]]
|-
| Gen 4 symmetric
| rowspan="3" | USB4 v2.0
| rowspan="3" | [[Pulse-amplitude modulation|PAM-3]]<ref>{{cite web |author=Team GraniteRiverLabs |date=2023-01-17 |title=Welcome to the 80Gpbs Ultra-High Speed Era of USB4 |publisher=GraniteRiverLabs Taiwan |url=https://www.graniteriverlabs.com/en-us/technical-blog/usb4-80-cio80 |url-status=live |archive-url=https://web.archive.org/web/20230221162539/https://www.graniteriverlabs.com/en-us/technical-blog/usb4-80-cio80 |archive-date=2023-02-21 |access-date=2023-02-21 |website=www.graniteriverlabs.com |language=en-us}}</ref>
11b/7t
| 2/2
| rowspan="3" | ~40.58{{efn|name=gen4ovrhd}}
| ~81.15
| ~80.46
| USB 80Gbps
| [[File:USB 80Gbps logo.svg|50px]]
|-
| Gen 4 asymmetric 3:1
| 3/1
| rowspan="2" | 3x:<br/>~121.725<br/>1x:<br/>~40.58
| rowspan="2" | 3x:<br/>~120.69<br/>1x:<br/>~40.23<br/>
| colspan=2 {{N/A}}{{efn|name=optAsymm}}
|-
| Gen 4 asymmetric 1:3
| 1/3
| colspan=2 {{N/A}}{{efn|name=optAsymm}}
|-
| rowspan="2" {{N/A}}
| style="white-space: nowrap;"| {{Abbr|TB3|Thunderbolt 3}} Gen 2x2
| rowspan="2" {{N/A}}
| 64b/66b
| 2/2
| 10.3125
| 20.625
| 20
| colspan="2" {{N/A}}
|-
| style="white-space: nowrap;"| {{Abbr|TB3|Thunderbolt 3}} Gen 3x2
| 128b/132b
| 2/2
| 20.625
| 41.25
| 40
| colspan="2" {{N/A}}
|}

{{notelist|refs=
{{efn|name=usbnaming| Names according to the newest specifications.}}
{{efn|name=diff10&nbsp;gbps| USB4 Gen 2 is different from USB3 Gen 2. They both signify the same signal rate of 10 Gbit/s, but use different encoding and differ on the electrical layer. They also have different requirements for signal quality.}}
{{efn|name=rs-fec| USB4 Gen 2 & 3 can use optional [[Reed–Solomon error correction|Reed–Solomon]] [[Error correction code#Forward error correction|forward error correction]] (RS FEC). In this mode, 12 × 16&nbsp;B (128&nbsp;bit) symbols are assembled together with 2&nbsp;B (12&nbsp;bit + 4&nbsp;bit reserved) synchronisation bits indicating the respective symbol types and 4&nbsp;B of RS FEC to allow to correct up to 1&nbsp;B of errors anywhere in the total 198&nbsp;B block.}}
{{efn|name=usb4single| USB4 is required to support dual-lane modes, but it uses single-lane operations during initialization of a dual-lane link; single-lane link can also be used as a fallback mode in case of a lane bonding error.}}
{{efn|name=optAsymm| Optional features of USB 80Gbps connections and devices.}}
{{efn|name=usb3gen1x2| USB3 Gen 1x2 connection requires both sides to be USB3 "20 Gbps" / Gen 2x2 capable, but fail to establish Gen 2 / 10 Gbit/s per wire-pair connections.}}
{{efn|name=netdatarate| Total data rate (1 direction) with encoding overhead removed.}}
{{efn|name=gen4ovrhd| Per spec, lines run at 25.6 GBaud. One symbol contains 1 trit of information. Encoding transforms each group of 11 bits into 7 trits. 7 trits give 2187 different values or <math>log_2 3 \approx 1.585</math> bits/trit. {{harvnb|USB4 Version 2.0 Specification|2023|at=p84, sec. 3.2}}}}
}}

Thunderbolt 3 Gen 2 and Gen 3 and the USB4 Gen 2 and Gen 3 modes use very similar signaling. However, Thunderbolt 3 runs at slightly higher speeds, called legacy speeds, compared to rounded speeds of USB4.<ref>{{cite web |title=How to Test and Troubleshoot USB4 |url=https://files.keysightevent.com/files/20211215/5992-3142.pdf |url-status=live |archive-url=https://web.archive.org/web/20220910201247/https://files.keysightevent.com/files/20211215/5992-3142.pdf |archive-date=10 September 2022 |access-date=25 July 2022}}</ref> It is driven slightly faster at 10.3125 Gbit/s (for Gen 2) and 20.625 Gbit/s (for Gen 3), as required by Thunderbolt specifications.

USB4 Gen 4 is normally referred to as a speed of "40 Gbps" or 40 Gbit/s, with the full connections based on it being referred to as 80, 120/40, 40/120 Gbit/s. But since the actual signaling is no longer binary, the actual raw bit rates no longer match those numbers exactly.

== USB4 capabilities by device type ==

=== USB4 hub ===
A USB4 hub is defined by having 1 USB4 {{abbr|UFP|Upstream Facing Port}} and one or more USB4 {{abbr|DFP|Downstream Facing Port}}.

=== USB4-based dock ===
A USB4-based dock is defined as a USB4 hub that also has more specialized outputs like HDMI or DP, but still keeping some USB4 DFP.

=== USB4 peripheral device ===
A USB4 peripheral device is defined by not having any USB4 DFP. This means devices that are colloquially called "USB-C hubs" may use USB4 to support the dynamic bandwidth sharing or higher bandwidths of USB4. But they are not USB4 hubs if they do not have any USB4 DFP. Not having any USB4 DFP allows the peripheral to only support exactly those USB4 features that it has uses for, potentially simplifying its implementation considerably.

{| class="wikitable" style="text-align:center;"
|+ USB4 feature support<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p17ff, sec. 2.1.1.4}}</ref>
! colspan="2" |Feature
! rowspan="2" |Host
! rowspan="2" |Hub (dock)
! rowspan="2" |Peripheral device
|-
!Type
!
|-
| rowspan="5" |USB4
connection
| "20 Gbps" (Gen 2x2) || {{yes}} || {{yes}} || {{yes}}
|-
| "40 Gbps" (Gen 3x2) || {{optional}} || {{yes}} || {{optional}}
|-
| "80 Gbps" (Gen 4 symm.) || {{optional}} || {{optional}} || {{optional}}
|-
| "120/40 Gbps" (Gen 4 3:1) || {{optional}} || {{optional}}{{efn|name=usb4asymmhub}} || {{optional}}
|-
| "40/120 Gbps" (Gen 4 1:3) || {{optional}} || {{optional}}{{efn|name=usb4asymmhub}} || {{optional}}
|-
| rowspan="6" |Tunneled
| USB3 "10 Gbps" (Gen 2x1) || {{yes}} || {{yes}} || {{optional}}
|-
| USB3 "20 Gbps" (Gen 2x2) || {{optional}} || {{optional}} || {{optional}}
|-
| USB3 Gen T (variable bandwidth){{efn|name=gentvar}}|| {{optional}} || {{optional}} || {{optional}}
|-
| DisplayPort || {{yes}} || {{yes}} || {{optional}}
|-
| PCI Express || {{optional}}{{efn|name=winusb4req}} || {{yes}} || {{optional}}
|-
| Host-to-host communications/
USB4 networking
| {{yes}} || {{yes}} || {{n/a}}
|-
| rowspan="7" |Native
| USB3 "5 Gbps" (Gen 1x1) || {{yes}} || {{yes}} || {{optional}}
|-
| USB3 "10 Gbps" (Gen 2x1) || {{yes}} || {{yes}} || {{optional}}
|-
| USB3 "20 Gbps" (Gen 2x2) || {{optional}} || {{optional}} || {{optional}}
|-
| USB 2.0
(Low-, Full-, High-Speed){{efn|name=usb2nevertunneled}}
| {{yes}} || {{yes}} || {{optional}}
|-
| DisplayPort Alternate Mode{{efn|name=usb4dpaltreq}} || {{yes}} || {{yes}} || {{optional}}
|-
| Thunderbolt Alternate Mode || {{optional}}{{efn|name=winusb4req}} || {{yes}} || {{optional}}
|-
| Other alternate modes || {{optional}} || {{optional}} || {{optional}}
|}

{{notelist|refs=
{{efn|name=winusb4req| Windows HLK requires any USB4 port support PCIe tunneling and TB3 compatibility. No minimum PCIe bandwidth requirements.<ref name="winhklusb4">{{Cite web |last=windows-driver-content |date=2022-05-18 |title=USB4 Systems PCIe Tunneling Support |url=https://learn.microsoft.com/en-us/windows-hardware/test/hlk/testref/7d627bf0-25f3-4564-b554-b2a3450e2bcf |access-date=2024-08-05 |website=learn.microsoft.com |language=en-us}}</ref>}}
{{efn|name=usb2nevertunneled| As with USB3, USB2 connection runs on separate wires from main (USB3/USB4) connection. Tunneling is not required as it runs in parallel on the cable.}}
{{efn|name=usb4dpaltreq| The USB4 specification makes no requirements on the minimum speed or capabilities of any DP output.}}
{{efn|name=usb4asymmhub| Even for "80 Gbps" USB4 hubs, supporting asymmetric connections (in either direction) is optional, but 80 Gbit/s support is a prerequisite for any asymmetric support.}}
{{efn|name=gentvar| USB3 Gen T tunneling has defined bandwidth options. They match the total USB4 speed numbers 10,20,40,80 and even asymmetric 40/120,120/40 connections. USB4 v2 specification, p536, tab.9-19}}
}}

== Cable compatibility==

The Type-C standard supports cable backward/downward compatibility in many situations. The compatibility typically only breaks between the different families of standards (USB 2.0, USB 3.2, USB4). The USB4 standard mandates that classic active or hybrid active cables still have vast backward compatibility support, so as to behave as if they were regular, passive cables in the eyes of the consumer.<ref>{{harvnb|Type-C Cable and Connector Specification|2023|at=p261 para. 3}}</ref> But forward compatibility is limited for active cables. Only Optically Isolated Active Cables (OIAC), that should be clearly distinguishable by price, design, cable thickness, and advertising, is allowed to strip most of the backwards compatibility away.

The Gen 4 transmission mode with PAM-3 uses very different signaling to previous modes. Every active component needs to explicitly support this new signaling, but it stays within all signal quality requirements of existing, passive Gen 3 cables (USB4 and TB3).

=== Cable naming and relation to specification versions ===
USB-IF intends only for the new bandwidth-based logos and names to be used with consumers.<ref>{{cite web |title=USB Branding Session 2019 |website=usb.org |date=2020-02-07 |access-date=2024-07-08 |url=https://usb.org/sites/default/files/D1T2-1%20-%20USB%20Branding%20Session.pdf |language=en |at=p16 }}</ref> For cables, the type (passive, active) and the highest supported bandwidth are usually enough to uniquely identify a cable and its supported features. Although some active types make clear distinctions where further details on the type are required. Formally, a cable type and properties are defined by a distinct specification version, which was used during the development/design of said cable model, so each cable would be a valid and possibly certified cable according to a specific set of USB specification versions, like "Type-C 2.3, USB 3.2, USB4 Version 2.0". But the standard is also designed to be interoperable, in that a newer specification version typically adds new modes of operation, new cable types, but does not restrict previously existing things. Because that would make existing things incompatible with new products. For this purpose, even the older USB logos and labels did not include a specification version, but only stated [[:File:Certified SuperSpeed Plus USB 10 Gbps Logo.svg|"Certified USB SuperSpeed+ 10 Gbps"]]. This logo identified cables that could support the 10 Gbit/s connection speeds of USB3 across both the USB 3.1 and USB 3.2 version, because the requirements for the cables have not changed. Thus, a precise specification version is usually not relevant and would not make a difference.

Transmission modes such as Gen2x2 are also irrelevant to cables, as valid cables are either full-featured, having all the high speed wire-pairs for up to dual-lane connections at the stated speed or they are USB2-only or some other specific and restrictive type, as listed below.

=== USB4 cable compatibility ===
{{mw-datatable}}
{| class="wikitable hover-highlight"
|+ Overview of passive<ref>{{harvnb|Type-C Cable and Connector Specification|2023|at=p42, Tab 3-1}}</ref><ref>{{cite web |title=How to Beat the Maximum USB Cable Length Limit |url=https://blog.tripplite.com/usb-cable-max-length |access-date=2024-03-14 |website=blog.tripplite.com |language=en}}</ref> and active Type-C cables<ref>{{harvnb|Type-C Cable and Connector Specification|2023|at=p261 sec. 6}}</ref> and their USB4 support
! colspan="2" |Cable type
! rowspan="2" |Speed
! rowspan="2" |Marketing names
! rowspan="2" |Max. USB4 bit rate
! rowspan="2" |Expected max. cable length{{efn|name=lengthestimates}}
! colspan="4" |Other support
! rowspan="2" |Power
|-
!
!Remarks
!USB2
!USB3
!TB3
!DP
|-
|{{verth|USB2}}
|{{n/a}}
|
|Hi-Speed USB
|{{na}}
|≤ 4m
|{{yes}}
|{{no}}
|{{no}}
|{{no}}
| rowspan="8" |USB PD:
60W

or

100W

or

240W
|-
| rowspan="3" {{verth|Full-Featured passive}}
| rowspan="2" {{n/a}}
|Gen 1
|USB 5Gbps
|{{some|20 Gbit/s}}{{efn|name=gen1usb4}}
|≤ 2m
|{{yes}}
|{{some|5 Gbit/s}}
|{{no}}
| rowspan="2" {{yes}}{{efn|name=dpspeed}}
|-
|Gen 2
|USB 20Gbps
(USB 10Gbps deprecated)
|{{some|20 Gbit/s}}
|≤ 1m
|{{yes}}
|{{yes}}
|{{some|20 Gbit/s}}
|-
|(incl. passive TB4 & TB5)
|Gen 3 & Gen 4
|USB 40Gbps
USB 80Gbps
|{{yes|80 Gbit/s}}
(or asymm.)
|≤ 0.8m
|{{yes}}
|{{yes}}
|{{yes}}{{efn|name=usb4cabletb3backcompat}}
| rowspeed="2" {{yes}}{{efn|name=dpspeed}}{{efn|name=tbdpguarantees}}
|-
| rowspan="4" {{verth|Full-Featured active (also optical hybrid)}}
|{{n/a}}
|Gen 2
|USB 20Gbps
(USB 10Gbps deprecated)
|{{some|20 Gbit/s}}
| rowspan="4" |< 5m
|{{yes}}
|{{yes}}
|{{yes}}
| {{optional}}{{efn|name=dpspeedactive}}
|-
|(incl. active TB4)
|Gen 3
|USB 40Gbps
|{{yes2|40 Gbit/s}}
|{{yes}}
|{{yes}}
|{{yes}}
| rowspan="2" {{optional}}{{efn|name=dpspeedactive}}
TB up to 2m{{efn|name=tbdpguarantees}}
|-
|(incl. active TB5)
|Gen 4
|USB 80Gbps
|{{yes|80 Gbit/s}}
(or asymm.)
|{{yes}}
|{{yes}}
|{{yes}}
|-
|USB3 active
|Gen 2
|{{dunno}}
|{{na}}
|{{yes}}
|{{yes}}
|{{no}}
|{{optional}}
|-
| rowspan="3" {{verth|{{abbr|OIAC|Optically Isolated Active Cables}}}}
|USB3
|Gen 2
|{{dunno}}
|{{na}}
| rowspan="3" | ≤ 50m
| rowspan="3" {{optional|only if optical}}
| rowspan="3" {{some|Gen 2 only}} (10 / 20 Gbit/s)
|{{no}}
| rowspan="3" {{optional}}
| rowspan="3" {{n/a}}
|-
| rowspan="2" | USB4
|Gen 3
|{{dunno}}
|{{yes2|40 Gbit/s}}
| rowspan="2" {{optional}}
|-
|Gen 4
|{{dunno}}
|{{yes2|80 Gbit/s}}
(asymm. optional)
|-
| rowspan="4" {{verth|Thunderbolt 3}}
| rowspan="2" |passive
|Gen 2
|TB Logo without "3"
|{{some|20 Gbit/s}}
|≤ 2m
|{{yes}}
|{{some|only 5 Gbit/s when > 1m}}<ref>{{cite web |title=Cable Matters 107002 40 Gbps / 20 Gbps Thunderbolt 3 Cable |url=https://kb.cablematters.com/index.php?View=entry&EntryID=76 |website=kb.cablematters.com |access-date=12 August 2024 |date=2024-10-09 |quote=When connected to USB-C devices, the data rate can reach 10 Gbps (0.5m & 1m) and 5 Gbps (2m).}}</ref>
|{{some|20 Gbit/s}}
| rowspan="2" {{yes}}{{efn|name=dpspeed}}
| rowspan="3" |USB PD:
60W

or

100W
|-
|Gen 3
|TB Logo + "3"
|{{yes|80 Gbit/s}}
(or asymm.)<ref>{{harvnb|Type-C Cable and Connector Specification|2023|at=p246, fig. 5-1}}</ref>
|≤ 0.8m
|{{yes}}
|{{yes}}
|{{yes}}
|-
|active
|Gen 3
|TB Logo + "3"
|{{na}}{{efn|name=appletb3pro}}
|(longest available: 3m)
|{{yes}}
|{{rarely|(mostly no)}}<ref>{{cite web |title=USB-C Cables, Thunderbolt 3 Cables - How to tell them apart |url=https://archive.caldigit.com/Thunderbolt-3-USB-C-Type-C-Charge-Cable/ |website=archive.caldigit.com |publisher=CalDigit |access-date=8 August 2024}}</ref>
|{{yes}}
|{{rarely|(mostly no)}}<ref>{{cite web|title=How to select a Thunderbolt 3 cable? |date=11 May 2019 |url=https://www.chargerlab.com/how-to-select-a-thunderbolt-3-cable-2 |publisher=chargerlab.com |access-date=2024-08-08}}</ref>
|-
|optical<ref>{{cite web|title=Corning Thunderbolt™ 3 Optical Cable (40 Gb/s) |url=https://www.corning.com/microsites/coc/ocbc/Documents/OEM-062-A4-AEN.pdf |publisher=Corning |access-date=2024-08-08}}</ref>
|Gen 3
|TB Logo + "3"
|{{na}}
|{{dunno}}
|{{no}}
|{{no}}
|{{yes}}
|{{no}}
|{{n/a}}
|}

{{notelist|refs=
{{efn|name=gen1usb4| USB4 Gen 2 has less strict signal requirements than USB 3 Gen 2. Spec compliant USB3 Gen 1 cables should support USB4 Gen 2 / 20 Gbit/s connections}}
{{efn|name=dpspeed| No specific max. DP speed guaranteed by Type-C specification}}
{{efn|name=dpspeedactive| No specific max. DP speed guaranteed by Type-C specification. There are different implementations of active cable implementations that may behave differently.}}
{{efn|name=usb4cabletb3backcompat| USB4 launched with passive Gen 3 cables supporting TB3 40 Gbit/s on an electrical level, but where not mandated to identify in the historical way TB3 identified those cables (because that predates the existence of "Gen 3"). Early passive USB4 cables may thus not be identified as TB3 40 Gbit/s capable by old TB3 equipment predating the existence of USB4. This was fixed with a later revision.{{cite web|author-last=Leung |author-first=Benson |title=ECN to ensure full compatibility of USB4 cables with TB3 specification |date=May 2023 |url=https://www.reddit.com/r/UsbCHardware/comments/13418w7/comment/jie4jc0/ |access-date=2024-06-08 |language=en}}{{citation needed|reason=ECN|date=August 2024}}}}
{{efn|name=appletb3pro| The Apple TB3 Pro cable is one of the few active TB3 cables that supports DP and USB3. It is unclear if that is special behavior or the cable would be compatible to USB4 as well.{{cite web |title=Apple now sells a $129 Thunderbolt 3 Pro cable |url=https://www.theverge.com/2020/7/27/21339861/apple-thunderbolt-3-pro-cable-specs-price-available |website=theverge.com |date=27 July 2020 |publisher=The Verge |access-date=9 August 2024}}}}
{{efn|name=lengthestimates| Maximum cable lengths are not normative, but simply estimates of the USB specification, based on the expected physical limits of conventional copper cables.}}
{{efn|name=tbdpguarantees| TB4 & TB5 cables up to 2m length (active & passive) are "universal cables", including DP support. DP guarantees may only include the highest speeds covered by DP 1.4 for TB4 (HBR3) or DP 2.1 for TB5 (UHBR20).}}
}}

=== DP Alt Mode support for USB4 cables ===
The Type-C specification does not name specific DP speeds that it considers supported for passive cables where support is optional for active cables. The USB-C presentation on DP Alt mode<ref>{{cite web|title=VESA – DisplayPortTM Alternate Mode on USB-C® |url=https://www.usb.org/sites/default/files/D2T1-4%20-%20VESA%20DP%20Alt%20Mode%20over%20USB%20Type-C.pdf |access-date=2024-08-08 |at=p23 |date=2019-11-19}}</ref> calls out passive full-featured USB-C cables for their DisplayPort support and headroom for future DP speed increases. HBR3 was the highest available DP speed at the time.

Active cables may have additional complications, because the active electronics does not need to operate all high speed wire-pairs in the same direction for normal USB operations (but "80 Gbps" cables are mandated to support asymmetric connections, which includes at least some of the wire-pairs operating in either direction). Active cables can have further limitations, since the active electronics may only support specific signaling modes. There are 2 variants of active electronics. Linear ReDrivers only amplify the signal without any particular signaling mode or encoding in mind. ReTimers explicitly reconstruct the incoming signal for a higher quality result.

TB4 cables, even active ones, at least up to 2m in length, are guaranteed to support DP Alt mode. A specific maximum speed is also not mentioned, but the other requirements for TB4 all refer to DP 1.4 and its maximum speed of HBR3.<ref>{{cite web|url=https://www.thunderbolttechnology.net/sites/default/files/intel-thunderbolt4-announcement-press-deck.pdf |title=Intel Thunderbolt 4™ Announcement Press Deck |publisher=Intel |access-date=2024-08-08 |at=p9, p13}}</ref> TB5 renews the same guarantee<ref>{{cite web |title=Thunderbolt 5™ Press Deck|url=https://www.thunderbolttechnology.net/sites/default/files/TBT5%20Press%20Deck%20v3%20Final.pdf |website=thunderbolttechnology.net |publisher=Intel |access-date=9 August 2024}}</ref> for "80 Gbps" cables while referencing the DP 2.1 specification (up to UHBR20 speeds).

DP 2.1 aligned itself to the USB4 PHY layer, according to VESA, the creator of DisplayPort.<ref>{{cite web |title=VESA Releases DisplayPort 2.1 Specification |url=https://www.displayport.org/pr/vesa-releases-displayport-2-1-specification/ |access-date=2024-08-06}}</ref> It is unclear how complete this alignment is. However, the UHBR10 DP speed matches USB4 Gen 2 in bit rate and encoding, whereas the UHBR20 DP speed matches USB4 Gen 3 in bit rate and encoding. A USB and DP certification service lists USB Gen 1 cables ("5 Gbps") as supporting UHBR10 speeds, which would fit for having the same requirements as USB4 "20 Gbps" connections.<ref>{{cite web|title=Specification and Test Overview of DisplayPort™ 2.1 |url=https://www.graniteriverlabs.com/en-us/technical-blog/displayport-dp-2-1-overview |publisher=Granite River Labs |access-date=2024-08-08 |at=Ultra High Bit Rate in DisplayPort™ 2.1 |quote=}}</ref>

Anandtech reports<ref>{{cite web|title=DisplayPort Alt Mode 2.0 Spec Released: Defining Alt Mode for USB4 |url=https://www.anandtech.com/show/15752/displayport-alt-mode-20-spec-released |publisher=Anandtech |access-date=2024-08-08}}</ref> that "this also means that DP Alt Mode 2.0 should largely work with USB4-compliant cables, although VESA is being careful to avoid promising compatibility with all cables".

There are linear redrivers<ref>{{cite web |title=PI2DPX2020 |url=https://www.diodes.com/part/view/PI2DPX2020?BackID=237 |website=Diodes | date=2 March 2011 |access-date=2024-08-08}}</ref> and retimers<ref>{{cite web |title=KM864742 |url=https://www.nuvoton.com/products/high-speed-interface/usb4-re-timer/cable/km864742/ |publisher=Nuvoton |access-date=9 August 2024}}</ref> available that are advertised for USB4 Gen 3 speeds and all current DP speeds up to UHBR20 and including UHBR13.5.

== Thunderbolt compatibility ==
{{Main|Thunderbolt (interface)}}

=== Thunderbolt 3 ===

The USB4 specification states that a design goal is to "Retain compatibility with existing ecosystem of USB and Thunderbolt products." Compatibility with Thunderbolt 3 is required for USB4 hubs, where this is optional for USB4 hosts and USB4 peripheral devices.<ref>USB4 Specification V1.0 August 2019 Chapter 13: "A USB4 host and USB4 peripheral device may optionally support TBT3-Compatibility. If a USB4 host or USB4 peripheral device supports TBT3-Compatibility, it shall do so as defined in this chapter".</ref> Compatible products need to implement 40 Gbit/s mode, at least 15W of supplied power and a different clock. Implementers need to sign the license agreement and register a Vendor ID with Intel.<ref>{{cite web |url=https://usb.org/document-library/usb4tm-thunderbolt3tm-compatibility-requirements-specification |title=USB4 Thunderbolt3 Compatibility Requirements Specification – USB-F |access-date=13 November 2021 |archive-date=24 November 2021 |archive-url=https://web.archive.org/web/20211124133132/https://www.usb.org/document-library/usb4tm-thunderbolt3tm-compatibility-requirements-specification |url-status=live}}</ref>

The USB4 protocol is based on and related to the operating principles of Thunderbolt 3. The USB4 specification simply defines which features to disable, downgrade and which parameters to change to get to an implementation compatible with Thunderbolt 3.<ref>{{harvnb|USB4 Version 2.0 Specification|2023|at=p709ff, sec. 13 Interoperability with Thunderbolt 3 (TBT3) Systems}}</ref> This includes, for example: limitation to daisy-chain topology (a hub must expose at most one USB4 DFP), downgrade of DP capabilities to DP 1.2, disabling/replacing the USB3 tunnel with an integrated PCIe-USB3 Host controller attached via PCIe tunnel, switching back to the previous, slightly higher signaling rate of TB3 and its separate way of initiating a connection as an Alt Mode.

=== Thunderbolt 4 ===

During [[Consumer Electronics Show#2020|CES 2020]], USB-IF and Intel stated their intention to allow USB4 products that optionally support any or all of the same functionality as [[Thunderbolt (interface)#Thunderbolt 4|Thunderbolt 4]] products. The first products compatible with USB4 were Intel's [[Tiger Lake]] processors, with more devices appearing around the end of 2020.<ref>{{cite web |url=https://www.engadget.com/2019-09-03-usb4-devices-next-year.html |title=USB4 devices are clear to roll out next year |website=Engadget |date=3 September 2019 |access-date=28 April 2020 |archive-date=24 November 2021 |archive-url=https://web.archive.org/web/20211124132956/https://www.engadget.com/2019-09-03-usb4-devices-next-year.html |url-status=live}}</ref><ref>{{cite web |url=https://www.pcbuildersclub.com/en/2019/06/first-usb-4-devices-to-be-launched-at-the-end-of-2020/ |title=First USB 4 devices to be launched at the end of 2020 |author-first=Florian |author-last=Maislinger |date=14 June 2019 |access-date=28 April 2020 |archive-date=24 November 2021 |archive-url=https://web.archive.org/web/20211124151515/https://www.pcbuildersclub.com/en/2019/06/first-usb-4-devices-to-be-launched-at-the-end-of-2020/ |url-status=live}}</ref>

Thunderbolt 4 is an implementation of USB4 "40 Gbps". Thunderbolt 4 mandates some features that are optional in USB4, including backwards compatibility to Thunderbolt 3, minimum PCIe ("32 Gbps") and DP capabilities (2 DP tunnels, "4K60 each", HBR3+DSC).<ref>{{cite web|url=https://www.thunderbolttechnology.net/sites/default/files/intel-thunderbolt4-announcement-press-deck.pdf |title=Intel Thunderbolt 4 Announcement Press Deck |website=thunderbolttechnology.net |publisher=Intel |access-date=2024-08-08 |at=p4}}</ref>

=== Thunderbolt 5 ===

Thunderbolt 5 is an implementation of USB4 "80 Gbps". It mandates even higher minimum PCIe ("64 Gbps") and DP capabilities (2 DP tunnels, "6K60 each", unclear min. DP speed). It also mandates support for asymmetric 120/40 Gbit/s connections from hosts to docks, but does not mention the reverse.<ref>{{cite web |title=Thunderbolt 5™ Press Deck|url=https://www.thunderbolttechnology.net/sites/default/files/TBT5%20Press%20Deck%20v3%20Final.pdf |website=thunderbolttechnology.net |publisher=Intel |access-date=9 August 2024 |at=p19}}</ref>
== Pinout ==
[[File:USB Type-C Receptacle Pinout.svg|thumb|upright=2.0|Type-C receptacle pinout (end-on view)]]USB4 has 24 pins in a symmetrical USB Type-C shell. USB4 has 12 A pins on the top and 12 B pins on the bottom.<ref>{{cite web |date=2020-02-18 |title=The Relationship Between USB4 and the USB Type-C Connector |url=https://www.totalphase.com/blog/2020/02/usb4-and-usb-type-c-connector/ |access-date=2022-04-05 |website=Total Phase Blog |language=en |archive-date=10 September 2022 |archive-url=https://web.archive.org/web/20220910201251/https://www.totalphase.com/blog/2020/02/usb4-and-usb-type-c-connector/ |url-status=live}}</ref>

USB4 has two lanes of [[Differential signalling|differential]] SuperSpeed pairs. Lane one uses TX1+, TX1−, RX1+, RX1− and lane two uses TX2+, TX2−, RX2+, RX2−. USB4 transfers signals at 20 Gbit/s per lane. USB4 also keeps the differential D+ and D− for [[USB 2.0]] transfer.<ref>{{cite web |title=USB4 Specification |url=https://www.usb.org/document-library/usb4r-specification |access-date=2022-04-05 |website=www.usb.org |archive-date=14 April 2022 |archive-url=https://web.archive.org/web/20220414181705/https://www.usb.org/document-library/usb4r-specification |url-status=live}}</ref>

The CC configuration channels have roles of creating a relationship between attached ports, detecting plug orientation due to the reversible USB Type-C shell, discovering the VBUS power supply pins, determining the lane ordering of the SuperSpeed lanes and, finally, the USB protocol makes the CC configuration channel responsible for entering USB4 operation.<ref>{{cite web |author-last=Leung |author-first=Benson |date=2018-11-19 |title=USB Type-C's Configuration Channel |url=https://medium.com/@leung.benson/usb-type-c-s-configuration-channel-31e08047677d |access-date=2022-04-05 |website=Medium |language=en |archive-date=5 April 2022 |archive-url=https://web.archive.org/web/20220405163245/https://medium.com/@leung.benson/usb-type-c-s-configuration-channel-31e08047677d |url-status=live}}</ref>

{| class="wikitable" style="display: inline-table;"
|+ Type-C receptacle A pin layout
! scope="col" | Pin
! scope="col" | Name
! scope="col" | Description
|-
! scope="row" | A1
| GND
| Ground return
|-
! scope="row" | A2
| SSTXp1 ("TX1+")
| SuperSpeed differential pair #1, TX, positive
|-
! scope="row" | A3
| SSTXn1 ("TX1-")
| SuperSpeed differential pair #1, TX, negative
|-
! scope="row" | A4
| V<sub>BUS</sub>
| Bus power
|-
! scope="row" | A5
| CC1
| Configuration channel
|-
! scope="row" | A6
| Dp1
| [[USB 2.0]] differential pair, position 1, positive
|-
! scope="row" | A7
| Dn1
| USB 2.0 differential pair, position 1, negative
|-
! scope="row" | A8
| SBU1
| Sideband use (SBU)
|-
! scope="row" | A9
| V<sub>BUS</sub>
| Bus power
|-
! scope="row" | A10
| SSRXn2 ("RX2-")
| SuperSpeed differential pair #4, RX, negative
|-
! scope="row" | A11
| SSRXp2 ("RX2+")
| SuperSpeed differential pair #4, RX, positive
|-
! scope="row" | A12
| GND
| Ground return
|}

{| class="wikitable" style="display: inline-table;"
|+ Type-C receptacle B pin layout
! scope="col" | Pin
! scope="col" | Name
! scope="col" | Description
|-
! scope="row" | B12
|GND
|Ground return
|-
! scope="row" | B11
|SSRXp1
|SuperSpeed differential pair #2, RX, positive
|-
! scope="row" | B10
|SSRXn1
|SuperSpeed differential pair #2, RX, negative
|-
! scope="row" | B9
|V<sub>BUS</sub>
|Bus power
|-
! scope="row" | B8
|SBU2
|Sideband use (SBU)
|-
! scope="row" | B7
|Dn2
|USB 2.0 differential pair, position 2, negative{{efn|name=dp2.0-receptacle|There is only a single non-SuperSpeed differential pair in the cable. This pin is not connected in the plug/cable.}}
|-
! scope="row" | B6
|Dp2
|USB 2.0 differential pair, position 2, positive{{efn|name=dp2.0-receptacle}}
|-
! scope="row" | B5
|CC2
|Configuration channel
|-
! scope="row" | B4
|V<sub>BUS</sub>
|Bus power
|-
! scope="row" | B3
|SSTXn2
|SuperSpeed differential pair #3, TX, negative
|-
! scope="row" | B2
|SSTXp2
|SuperSpeed differential pair #3, TX, positive
|-
! scope="row" | B1
|GND
|Ground return
|}
{{notelist}}

==Software support==
USB4 is supported by:

* [[Linux kernel]] 5.6, released on 29 March 2020<ref>{{cite web |url=https://www.phoronix.com/scan.php?page=news_item&px=Linux-5.6-Released |title=Linux 5.6 Kernel Released With WireGuard, USB4, New AMD + Intel Hardware Support – Phoronix |website=Phoronix.com |access-date=28 April 2020 |archive-date=2 November 2021 |archive-url=https://web.archive.org/web/20211102223627/https://www.phoronix.com/scan.php?page=news_item&px=Linux-5.6-Released |url-status=live}}</ref>
* [[macOS]] [[macOS Big Sur|Big Sur (11.0)]], released on 12 November 2020<ref>{{cite web |url=https://www.apple.com/newsroom/2020/11/introducing-the-next-generation-of-mac/ |title=Introducing the next generation of Mac |website=apple.com |date=10 November 2020 |access-date=13 November 2020 |archive-date=1 March 2021 |archive-url=https://web.archive.org/web/20210301173940/https://www.apple.com/newsroom/2020/11/introducing-the-next-generation-of-mac/ |url-status=live}}</ref>
* [[Windows 11]], released with support for USB4 Version 1.0 on 5 October 2021<ref>{{cite web |title=Introduction to the USB4 connection manager in Windows |url=https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/usb4-intro-to-connection-manager |access-date=2021-11-03 |website=docs.microsoft.com |date=3 September 2021 |language=en-us |archive-date=3 November 2021 |archive-url=https://web.archive.org/web/20211103200955/https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/usb4-intro-to-connection-manager |url-status=live}}</ref>
** upgraded to USB4 Version 2.0 support including 80 Gbit/s around March 2024<ref>{{Cite web |title=February 29, 2024—KB5034848 (OS Builds 22621.3235 and 22631.3235) Preview - Microsoft Support |url=https://support.microsoft.com/en-us/topic/february-29-2024-kb5034848-os-builds-22621-3235-and-22631-3235-preview-5b718126-82b1-4e14-bf01-da3500a3fc88 |access-date=2024-08-05 |website=support.microsoft.com}}</ref>

=== Connection manager ===
Connection manager is the part of a USB4 host that manages connections across the entire USB4 topology, establishing of tunnels, handling any bandwidth reservations and data prioritization, like which DP tunnels can be established and at what speed. The USB4 driver in Windows 11 implements native OS support of USB4, where the connection manager is part of a driver that only works with matching controllers. Older controllers had the connection manager implemented inside their firmware and thus required far less support from the OS.

On Linux, the USB4 and Thunderbolt driver (named "thunderbolt") supports both firmware-managed and also OS-managed controllers via the same tools.

==Hardware support==
Brad Saunders, CEO of the USB Promoter Group, anticipates that most PCs with USB4 will support Thunderbolt 3, but for phones the manufacturers are less likely to implement Thunderbolt 3 support.<ref name="auto">{{cite web |url=https://www.tomshardware.com/news/usb-4-faq,38766.html |title=USB 4: Everything We Know So Far |author-first=Avram |author-last=Piltch |website=Tom's Hardware |date=20 April 2021 |access-date=30 April 2020 |archive-date=30 June 2021 |archive-url=https://web.archive.org/web/20210630140440/https://www.tomshardware.com/news/usb-4-faq,38766.html |url-status=live}}</ref>

On 3 March 2020, [[Cypress Semiconductor]] announced new Type-C power (PD) controllers supporting USB4, CCG6DF as dual port and CCG6SF as single port.<ref>{{cite web |url=https://www.anandtech.com/show/15567/cypress-announces-usb-32-usb4-controllers-ezpd-ccg6df-ccg6sf |title=Cypress Announces USB 3.2 & USB4-Ready Controllers: EZ-PD CCG6DF & CCG6SF |author-first=Anton |author-last=Shilov |website=www.anandtech.com |access-date=28 April 2020 |archive-date=6 December 2021 |archive-url=https://web.archive.org/web/20211206152338/https://www.anandtech.com/show/15567/cypress-announces-usb-32-usb4-controllers-ezpd-ccg6df-ccg6sf |url-status=live}}</ref>

In November 2020, Apple unveiled [[MacBook Air]] [[MacBook Air (Apple silicon)|(M1, 2020)]], [[MacBook Pro]] [[MacBook Pro (Apple silicon)|(13-inch, M1, 2020)]] and [[Mac Mini|Mac mini (M1, 2020)]], featuring two USB4 ports.

AMD also stated that [[Zen 3+]] (Rembrandt) processors will support USB4<ref>{{cite news |author-last=Cutress |author-first=Ian |title=AMD Announces Ryzen 6000 Mobile CPUs for Laptops: Zen3+ on 6nm with RDNA2 Graphics |url=https://www.anandtech.com/show/17166/amd-announces-ryzen-6000-mobile-cpus-for-laptops-zen3-on-6nm-with-rdna2-graphics |access-date=26 July 2022 |publisher=Anandtech |date=4 January 2022 |archive-date=25 June 2022 |archive-url=https://web.archive.org/web/20220625234326/https://www.anandtech.com/show/17166/amd-announces-ryzen-6000-mobile-cpus-for-laptops-zen3-on-6nm-with-rdna2-graphics/ |url-status=live}}</ref> and released products do have this feature after a chipset driver update.<ref>{{cite web |author-last=Klotz |author-first=Aaron |title=AMD Introduces USB 4 Support in Chipset Update for Ryzen 6000 Mobile (Updated) |url=https://www.tomshardware.com/news/amd-usb4-chipset-driver-update-for-ryzen-6000 |website=Tom's Hardware |language=en |date=28 June 2022}}</ref> However, AMD has only announced support for USB 3.2 Gen 2x2 in [[Zen 4]] processors that were released in September 2022.<ref>
{{cite news |author-last=Bonshor |author-first=Gavin |title=AMD Ryzen 7000 Announced: 16 Cores of Zen 4, Plus PCIe 5 and DDR5 for Socket AM5, Coming This Fall |url=https://www.anandtech.com/show/17399/amd-ryzen-7000-announced-zen4-pcie5-ddr5-am5-coming-fall |access-date=26 July 2022 |publisher=Anandtech |date=23 May 2022 |archive-date=26 July 2022 |archive-url=https://web.archive.org/web/20220726130535/https://www.anandtech.com/show/17399/amd-ryzen-7000-announced-zen4-pcie5-ddr5-am5-coming-fall |url-status=live}}</ref><ref>{{cite web |title=AMD confirms Zen4 & Ryzen 7000 series lineup: Raphael in 2022, Dragon Range and Phoenix in 2023 |url=https://videocardz.com/newz/amd-confirms-zen4-ryzen-7000-series-lineup-raphael-in-2022-dragon-range-and-phoenix-in-2023 |access-date=2022-11-29 |website=VideoCardz.com |language=en-US}}</ref> Intel supported Thunderbolt 3 and USB-C with their 8th generation mobile processors in 2018. For example, the Lenovo P52 has dual TB3 ports on the rear. TB/USB has evolved as Intel is able to refine logic design.

{{mw-datatable}}
{| class="wikitable"
|+ Known USB4 Controllers
! {{verth|Manufacturer}}
!Controller
!Family
!Type
!{{verth|native managed{{efn|name=usb4natmgmt}}}}
!{{verth|USB4 ver.}}
!{{verth|Speed Gbit/s}}
!USB4 Ports
(up / down)
!DP In / out
protocol
adapters{{efn|name=dpInOutProtAdptrs}}
!USB3
Gbit/s
!PCIe{{efn|name=hwcapusb4pcie}}
!{{verth|TB3 compat.}}
!Other ports
!Certified
|-
| rowspan="13" {{verth|Intel}}
|JHL8540<ref>{{Cite web |title=Intel JHL8540 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/193684/intel-jhl8540-thunderbolt-4-controller/specifications.html}}</ref>
|Maple Ridge
|Host
|{{no}}
| rowspan="3" |{{0}}1
| rowspan="5" |{{0}}40
|2 dn
|2 in
DP 1.4
(up to HBR3)
|10
(integ. ctrl.)
|x4 Gen 3 ("32 Gbit/s")
| rowspan="17" {{yes}}
|{{N/A}}
| rowspan="5" |TB4
|-
|JHL8440<ref>{{Cite web |title=Intel JHL8440 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/189982/intel-jhl8440-thunderbolt-4-controller/specifications.html}}</ref>
|Goshen Ridge
|Hub / Peri.
| rowspan="2" {{N/A}}
|1 up,
3 dn
|2 out
DP 1.4
(up to HBR3)
|10
(hub, integ. ctrl.)
|(32 Gbit/s)
|PCIe x1 Gen 3 dn,
1 USB3 dn
|-
|JHL8140<ref>{{Cite web |title=Intel JHL8140 USB4 Controller leak / review |url=https://www.reddit.com/r/UsbCHardware/comments/10q98lo/intel_hoover_ridge_jhl8140_usb4tb4_endpoint/}}</ref>
|Hoover Ridge
|Peri.
|1 up
|2 out
DP 1.4
(up to HBR3)
|10
(hub, integ ctrl.)
| {{N/A}}
|3 USB3/DP down,
1 USB3 dn
|-
|JHL9450<ref>{{Cite web |title=Intel JHL9540 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/225917/intel-jhl9540-thunderbolt-4-controller/specifications.html}}</ref>
| rowspan="4" |Barlow Ridge
|Host
|{{yes}}
| rowspan="4" |{{0}}2
|2 dn
|3 in
DP 2.1
(up to UHBR10, +UHBR20){{efn|name=barlowDpSpeeds}}
|20
(integ. ctrl.)
|x4 Gen 4 ("64 Gbit/s")
|1 DP out{{efn|name=barlowHostDpOut}}
|-
|JHL9440<ref>{{Cite web |title=Intel JHL9440 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/225918/intel-jhl9440-thunderbolt-4-accessory-controller/specifications.html}}</ref>
|Hub / Peri.
|{{N/A}}
|1 up,
3 dn
|3 out
2 in
DP 2.1
(up to UHBR10, +UHBR20){{efn|name=barlowDpSpeeds}}
|20
(hub, integ. ctrl.)
|x4 Gen 4 ("64 Gbit/s")
|2 DP in,
1 USB3 dn
|-
|JHL9580<ref>{{Cite web |title=Intel JHL9580 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/225921/intel-jhl9580-thunderbolt-5-controller/specifications.html}}</ref><ref>{{Cite web |title=Barlow Ridge Leak |url=https://videocardz.com/newz/intel-barlow-bridge-thunderbolt-5-controller-for-arrow-lake-s-cpus-detailed-enabling-pcie-gen4x4-for-external-gpus}}</ref>
|Host
|{{yes}}
| rowspan="2" |{{0}}80
|2 dn
|3 in
DP 2.1
(up to UHBR10, +UHBR20){{efn|name=barlowDpSpeeds}}
|20
(integ. ctrl.)
|x4 Gen 4 ("64 Gbit/s")
|1 DP out{{efn|name=barlowHostDpOut}}
| rowspan="2" |TB5
|-
|JHL9480<ref>{{Cite web |title=Intel JHL9480 USB4 Controller Specifications |url=https://www.intel.com/content/www/us/en/products/sku/225919/intel-jhl9480-thunderbolt-5-accessory-controller/specifications.html}}</ref>
|Hub / Per.
|{{N/A}}
|1 up,
3 dn
|3 out
2 in
DP 2.1
(up to UHBR10, +UHBR20){{efn|name=barlowDpSpeeds}}
|20
(hub, integ. ctrl.)
|x4 Gen 4 ("64 Gbit/s")
|2 DP in,
1 USB3 dn
|-
|Tiger Lake<ref>{{Cite web |title=Intel Tiger Lake CPU Specifications |url=https://www.intel.com/content/www/us/en/content-details/631121/11th-generation-intel-core-processor-datasheet-volume-1-of-2.html}}</ref>
| rowspan="6" | CPU-integrated
| rowspan="7" |Host
| {{no}}
| rowspan="3" |{{0}}1
| rowspan="7" |{{0}}40
| rowspan="4" |up to
2 + 2 dn{{efn|name=usb4ctrlGroups}}
| rowspan="6" |2 in/group:
up to HBR3
|10
|(32 Gbit/s)
| rowspan="2" {{N/A}}
| rowspan="6" |TB4
|-
|Alder Lake<ref>{{Cite web |title=Intel Alder Lake CPU Specifications |url=https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/usb-c-sub-system/}}</ref>
| rowspan="6"  {{yes}}
|10{{efn|name=sharedUsb3}}
| rowspan="5" {{N/A}}
|-
|Raptor Lake<ref>{{Cite web |title=Intel Raptor Lake CPU Specifications |url=https://www.intel.com/content/www/us/en/content-details/743844/13th-generation-intel-core-and-intel-core-14th-generation-processors-datasheet-volume-1-of-2.html}}</ref>
|10
(20 internal){{efn|name=sharedUsb3}}
|native output:{{efn|name=usb4portNativeOut}}
DP UHBR10, +UHBR20,{{efn|name=barlowDpSpeeds}} USB3 20G
|-
|Meteor Lake<ref>{{Cite web |title=Intel Meteor Lake CPU Specifications |url=https://edc.intel.com/content/www/us/en/design/products/platforms/details/meteor-lake-u-p/core-ultra-processor-datasheet-volume-1-of-2/}}</ref>
| rowspan="3" {{dunno}}
| rowspan="3" |20{{efn|name=sharedUsb3}}
| rowspan="3" |native output:{{efn|name=usb4portNativeOut}}
DP UHBR10, +UHBR20{{efn|name=barlowDpSpeeds}}
|-
|Lunar Lake<ref>{{Cite web |title=Intel Lunar Lake CPU Specifications |url=https://www.intel.com/content/www/us/en/content-details/829568/intel-core-ultra-200v-series-processors-datasheet-volume-1-of-2.html}}</ref>
|up to
2 +1 dn{{efn|name=usb4ctrlGroups}}
|-
|Arrow Lake<ref>{{Cite web |title=Intel Arrow Lake CPU Specifications |url=https://edc.intel.com/content/www/us/en/design/products/platforms/details/arrow-lake-s/core-ultra-200s-series-processors-datasheet-volume-1-of-2/}}</ref>
|2 dn
|-
| {{verth|AMD}}
| AMD CPU-integrated{{Citation needed|date=December 2024}}
| {{N/A}}
| {{0}}1
| up to 1+1 dn{{efn|name=usb4ctrlGroups}}
| 2 in/port
up to HBR3
| 10
| {{N/A}}
| native output:{{efn|name=usb4portNativeOut}}
DP UHBR10
| {{dunno}}
|-
| rowspan="3" {{verth|Apple}}
| M1/2
| Apple USB4/TB3
| rowspan="3" | Host
| rowspan="3" {{dunno}}
| rowspan="2" |{{0}}1
| rowspan="2" |{{0}}40
| rowspan="3" {{dunno}}
| 1 in/port
up to HBR3
| rowspan="3" |10
| rowspan="3" {{N/A}}
| rowspan="3" {{N/A}}
| TB3
|-
| M1-3 Pro, Max, M4
| Apple TB4
| 2 in/port
up to HBR3
| TB4
|-
| M4 Pro/Max<ref>{{Cite web |title=MacRumors: Kensington Thunderbolt 5 Dock |url=https://forums.macrumors.com/threads/kensington-thunderbolt-5-dock-sd5000t5.2442676/page-2 |access-date=2024-12-23 |quote=AppleThunderboltDPInAdapterOS [...] Cached Local DP Capabilities = <15c72335> [...] AppleThunderboltDPInAdapterOS [...]}}</ref>
| Apple TB5
| {{0}}2
| {{0}}80
| 2 in/port
up to UHBR10, +UHBR20{{efn|name=barlowDpSpeeds}}
| TB5
|-
| rowspan="2" {{verth|Via}}
|VL830<ref>{{Cite web |title=Via VL830 USB4 Controller Specifications |url=https://www.via-labs.com/product_show.php?id=114}}</ref>
| rowspan="6" {{N/A}}
| rowspan="2" |Peri.
| rowspan="4" {{N/A}}
| rowspan="5" |{{0}}1
| rowspan="5" |{{0}}40
| rowspan="2" |1 up
| rowspan="2" |1 out: DP 1.4 (up to HBR3)
| rowspan="2" |10 (hub)
| rowspan="2" {{no}}
| rowspan="2" {{no}}
| rowspan="2" |5 USB3 dn,
1 USB2 dn
| {{N/A}}
|-
|VL832<ref>{{Cite web |title=Via VL832 USB4 Controller Specifications |url=https://www.via-labs.com/product_show.php?id=119}}</ref>
|USB4
|-
| rowspan="3" {{verth|Asmedia}}
|ASM2464PD<ref>{{Cite web |title=ASM2464PD USB4 Controller Specifications |url=https://www.asmedia.com.tw/product/802zX91Yw3tsFgm4/C64ZX59yu4sY1GW5/ASM2464PD}}</ref>
|Peri. / NVMe
|1 up
| rowspan="2" {{N/A}}
|20 (peripheral)
|x4 Gen 4 ("64 Gbit/s")
|{{yes}}
|(USB3 NVMe ctrl., only integ. PD)
|USB4, TB4
|-
|ASM2464PDX<ref>{{Cite web |title=ASM2464PDX USB4 Controller Specifications |url=https://www.asmedia.com.tw/product/bDFzXa0ip1YI7Wj1/C64ZX59yu4sY1GW5/ASM2464PD}}</ref>
|Peri. / NVMe
|1 up
|20 (peripheral)
|x4 Gen 4,
(bifurcat. x1)
| {{yes}}
|(USB3 NVMe ctrl.)
| {{dunno}}
|-
|ASM4242<ref>{{Cite web |title=ASM4242 USB4 Controller Specifications |url=https://www.asmedia.com.tw/product/e20zx49yU0SZBUH5/363Zx80yu6sY3XH2/ASM424}}</ref>
|Host
|{{yes}}
|2 dn
|2 in: DP 1.4 (up to HBR3)
|20 (integ. ctrl.)
|x4 Gen 4 ("64 Gbit/s")
|{{yes}}
|{{N/A}}
|USB4,
TB4
|-
|{{verth|Realtek}}
|RTX5490<ref>{{Cite web |title=RTS5490 Multi-Port USB4 Hub Router Controller |url=https://www.realtek.com/Product/ProductHitsDetail?id=4426&menu_id=643}}</ref><ref>{{Cite web |title=RealTek RTS5490 USB4 hub controller port analysis |url=https://dancharblog.wordpress.com/2023/06/05/realtek-rts5490-controller-downstream-port-analysis/}}</ref><!-- This source mainly shows Realteks press material exhibited Computex 2023 about the controller -->
|Peri. / Hub
|{{N/A}}
|{{dunno|2?}}
|{{0}}40
|2 dn
|USB4 up/dn: UHBR20, ?
|20 (hub, integ. ctrl.)
|{{dunno}}
|{{yes}}
|2 USB3 20G, 1 DP UHBR20
|{{N/A}}
|}

{{notelist|refs=
{{efn|name=usb4natmgmt| Host controller is not managing itself with onboard firmware, but via ACPI and USB4 standard with generic OS drivers, such as Windows 11 USB4 drivers. Only applicable to host controllers. All other controllers have always been managed by the host's connection 
 manager, no matter if that is implemented in firmware or by the OS.}}
{{efn|name=hwcapusb4pcie| Main PCIe port of the controller. Not applicable for CPU-integrated host controllers. If PCIe is only used internal to the controller, PCIe throughput specifications are rarely given.}}
{{efn|name=dpInOutProtAdptrs |[[USB4#Protocol input/output adapters|Protocol adapters]] are what converts between a tunnel and a connection external to USB4. DP In adapters map directly to some input from a GPU. DP Out adapters may be shared across multiple physical outputs, in which case they limit how many can be used at the same time.}}
{{efn|name=usb4portNativeOut| What the respective USB4 ports can output directly, instead of tunneled through USB4. Can be higher than tunneled support, as not limited by the USB4 specification and technically independent of USB4 operations/connections.}}
{{efn|name=barlowHostDpOut |Unclear how much the output can do / be used for yet. Per leak "side port", may only be a passthrough of the third DP input}}
{{efn|name=barlowDpSpeeds |Supports UHBR10 and all lower speeds. And UHBR20, while not supporting UHBR13.5 speeds. UHBR10 and UHBR20 are aligned to USB4 Gen 2 and Gen 3 respectively, UHBR13.5 is not aligned to any existing USB4 signaling.}}
{{efn|name=usb4ctrlGroups |"2+2" indicates 2 separate dual-port USB4 host routers. But because integrated into the CPU, can share functionality that is not technically part of USB4 host router, like USB3. Systems may share a common USB3 controller, supplying 1 USB3 root port per USB4 port, similar with PCIe ports.}}
{{efn|name=sharedUsb3 |USB3 controller shared across all integrated USB4 ports}}
}}

==References==

{{Reflist}}

==Specification References==
<!-- Need not to be a separate section, but exists so we can cite to the same spec document multiple times, with different pages and sections without everytime spamming a new full reference or using inline pages. See https://en.wikipedia.org/wiki/Help:References_and_page_numbers#Shortened_footnotes. If this is valid, then references to USB specs should probably be unified -->
{{refbegin}}
* {{Cite web |title=USB Type-C® Cable and Connector Specification Release 2.3 {{!}} USB-IF |url=https://usb.org/document-library/usb-type-cr-cable-and-connector-specification-release-23 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|Type-C Cable and Connector Specification|2023}} |publisher=USB-IF}}
* {{Cite web |title=USB4® Specification v2.0 {{!}} USB-IF |url=https://usb.org/document-library/usb4r-specification-v20 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB4 Version 2.0 Specification|2023}} |publisher=USB-IF}}
** {{Cite web |title=USB4® Specification v2.0, Adopters Agreement {{!}} USB-IF |url=https://usb.org/document-library/usb4r-specification-v20 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB4 Version 2.0 Specification Adopters Agreement|2023}} |publisher=USB-IF}}
** {{Cite web |title=USB4® Specification v2.0, Connection Manager Guide {{!}} USB-IF |url=https://usb.org/document-library/usb4r-specification-v20 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB4 Version 2.0 Specification Connection Manager Guide|2023}} |publisher=USB-IF}}
** {{Cite web |title=USB4® Specification v2.0 Inter-Domain Service {{!}} USB-IF |url=https://usb.org/document-library/usb4r-specification-v20 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB4 Version 2.0 Specification Inter-Domain Service|2023}} |publisher=USB-IF}}
* {{Cite web |title=USB Power Delivery {{!}} USB-IF |url=https://usb.org/document-library/usb-power-delivery |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB Power Delivery Specification|2023}} |publisher=USB-IF}}
* {{Cite web |title=USB 2.0 Specification {{!}} USB-IF |url=https://usb.org/document-library/usb-20-specification |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB 2.0 Specification|2024}}}}
* {{Cite web |title=USB 3.2 Revision 1.1 - June 2022 {{!}} USB-IF |url=https://usb.org/document-library/usb-32-revision-11-june-2022 |access-date=2024-08-05 |website=usb.org |ref={{sfnRef|USB 3.2 Specification|2022}} |publisher=USB-IF}}
{{refend}}

==External links==
* [https://www.usb.org/usb4 USB4 | USB-IF]
* [https://www.usb.org/taxonomy/term/61 USB4 Taxonomy | USB-IF]
* Current USB specifications can be downloaded from [https://www.usb.org/documents usb.org]:
* [https://www.youtube.com/watch?v=Nax50U18iyo Podcast with Jit Lim] from [[Keysight]], 2019-11-21

{{USB}}

[[Category:USB|#4]]