View source for System on a chip

{{Use mdy dates|date=May 2022}}
{{Short description|Micro-electronic component}}
{{Use American English|date=October 2018}}
[[File:Apple M1.jpg|thumb|right|[[Apple M1]] system on a chip]]
[[File:Raspi 15807388763 6d259773fb o.png|thumb|A system on a chip from [[Broadcom]] in a [[Raspberry Pi]]]]

A '''system on a chip''' or '''system-on-chip''' ('''SoC''' {{IPAc-en|,|ˈ|ɛ|s|oʊ|s|iː}}; pl. ''SoCs'' {{IPAc-en|,|ˈ|ɛ|s|oʊ|s|iː|z}}) is an [[integrated circuit]] that integrates most or all components of a [[computer]] or [[Electronics|electronic system]]. These components usually include an on-chip [[central processing unit]] (CPU), [[computer memory|memory]] interfaces, [[input/output]] devices and interfaces, and [[computer data storage#Secondary storage|secondary storage]] interfaces, often alongside other components such as a [[Wi-Fi]] receiver and a [[graphics processing unit]] (GPU) &ndash; all on a single [[wafer (electronics)|substrate]] or microchip.<ref>{{Cite web|url=https://www.networkworld.com/article/3154386/7-dazzling-smartphone-improvements-with-qualcomms-snapdragon-835-chip.html|title=7 dazzling smartphone improvements with Qualcomm's Snapdragon 835 chip|first=Agam|last=Shah|date=January 3, 2017|website=Network World}}</ref> SoCs may contain [[digital signal (electronics)|digital]] and also [[analog signal|analog]], [[mixed-signal integrated circuit|mixed-signal]] and often [[radio frequency]] [[signal processing]] functions (otherwise it may be considered on a discrete application processor).

High-performance SoCs are often paired with dedicated and physically separate memory and secondary storage (such as [[LPDDR]] and [[Universal Flash Storage|eUFS]] or [[eMMC]], respectively) chips that may be layered on top of the SoC in what is known as a [[package on package]] (PoP) configuration, or be placed close to the SoC. Additionally, SoCs may paired with smaller separate chips, such as baseband [[modem]]s.<ref name=QS_1>{{cite web| title=Qualcomm's Snapdragon X60 promises smaller 5G modems in 2021| author=Amadeo, R.| url=https://arstechnica.com/gadgets/2020/02/qualcomms-snapdragon-x60-promises-smaller-5g-modems-in-2021/?amp=1| website=Ars Technica| publisher=[[Conde Nast]]| date=18 February 2020| access-date=17 December 2023}}</ref>

An SoC usually [[System integration|integrates]] a [[microcontroller]], [[microprocessor]] or perhaps several processor cores with peripherals like a [[GPU]] and a [[Wi-Fi]] receiver and more [[coprocessor]]s. Similar to how a microcontroller integrates a microprocessor with peripheral circuits and memory, an SoC can be seen as integrating a microcontroller with even more advanced [[peripheral]]s.

Compared to a multi-chip architecture, an SoC with equivalent functionality will have reduced [[power consumption]] as well as a smaller [[Die (integrated circuit)|semiconductor die]] area. This comes at the cost of reduced [[Interchangeable parts|replaceability]] of components. By definition, SoC designs are fully or nearly fully integrated across different component [[Modularity|modules]]. For these reasons, there has been a general trend towards tighter integration of components in the [[Semiconductor industry|computer hardware industry]], in part due to the influence of SoCs and lessons learned from the mobile and embedded computing markets. 

SoCs are very common in the [[mobile computing]] (as in [[smart device]]s such as [[smartphones]] and [[tablet computer]]s) and [[edge computing]] markets.<ref>Pete Bennett, [[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1276973 The why, where and what of low-power SoC design]." December 2, 2004. Retrieved July 28, 2015.</ref><ref>{{Cite web|url=https://www.design-reuse.com/articles/42705/power-management-for-iot-soc-development.html|title=Power Management for Internet of Things (IoT) System on a Chip (SoC) Development|last=Nolan|first=Stephen M.|website=Design And Reuse|access-date=2018-09-25}}</ref>

== Types ==
[[Image:ARMSoCBlockDiagram.svg|upright=1.3|thumb|[[Microcontroller]]-based system on a chip]]
In general, there are three distinguishable types of SoCs:
* SoCs built around a [[microcontroller]],
* SoCs built around a [[microprocessor]], often found in mobile phones;
* Specialized [[application-specific integrated circuit]] SoCs designed for specific applications that do not fit into the above two categories.

== Applications ==
SoCs can be applied to any computing task. However, they are typically used in mobile computing such as tablets, smartphones, smartwatches, and netbooks as well as [[embedded system]]s and in applications where previously [[microcontroller]]s would be used.

=== Embedded systems ===
Where previously only microcontrollers could be used, SoCs are rising to prominence in the embedded systems market. Tighter system integration offers better reliability and [[Mean time between failures|mean time between failure]], and SoCs offer more advanced functionality and computing power than microcontrollers.<ref>{{Cite news|url=https://www.embedded.com/design/mcus-processors-and-socs/4419584/Is-a-single-chip-SOC-processor-right-for-your-embedded-project-|title=Is a single-chip SOC processor right for your embedded project?|work=Embedded|access-date=2018-10-13|language=en}}</ref> Applications include [[AI accelerator|AI acceleration]], embedded [[machine vision]],<ref>{{Cite web|url=https://www.imveurope.com/news/qualcomm-launches-socs-embedded-vision|title=Qualcomm launches SoCs for embedded vision {{!}} Imaging and Machine Vision Europe|website=www.imveurope.com|language=en|access-date=2018-10-13}}</ref> [[data collection]], [[telemetry]], [[vector processing]] and [[ambient intelligence]]. Often embedded SoCs target the [[internet of things]], multimedia, networking, telecommunications and [[edge computing]] markets. Some examples of SoCs for embedded applications include:

* [[AMD]]
** Zynq 7000 SoC
** Zynq UltraScale+ MPSoC
** Zynq UltraScale+ RFSoC
** Versal Adaptive SoC

=== Mobile computing ===
[[File:Nokia-9110-4.jpg|thumb|System on a chip [[AMD Élan]] SC450 in [[Nokia 9000 Communicator]]]]
[[Mobile computing]] based SoCs always bundle processors, memories, on-chip [[Cache (computing)|caches]], [[wireless networking]] capabilities and often [[digital camera]] hardware and firmware. With increasing memory sizes, high end SoCs will often have no memory and flash storage and instead, the memory and [[flash memory]] will be placed right next to, or above ([[package on package]]), the SoC.<ref>{{Cite web|url=https://www.ifixit.com/Teardown/Samsung+Galaxy+S10+and+S10e+Teardown/120331|title=Samsung Galaxy S10 and S10e Teardown|date=March 6, 2019|website=iFixit}}</ref> Some examples of mobile computing SoCs include:

* [[Samsung Electronics]]: [[List of Samsung System on Chips|list]], typically based on [[ARM architecture family|ARM]]
** [[Exynos]], used mainly by Samsung's [[Samsung Galaxy|Galaxy]] series of smartphones
* [[Qualcomm]]:
** [[Qualcomm Snapdragon|Snapdragon]] ([[List of Qualcomm Snapdragon systems-on-chip|list]]), used in many smartphones. In 2018, Snapdragon SoCs were being used as the backbone of [[Laptop|laptop computers]] running [[Windows 10]], marketed as "Always Connected PCs".<ref name=":3">{{Cite news|url=https://www.windowscentral.com/arm-going-after-intel-new-chip-roadmap-through-2020|title=ARM is going after Intel with new chip roadmap through 2020|work=Windows Central|access-date=2018-10-06|language=en}}</ref><ref name=":4">{{Cite web|url=https://www.microsoft.com/en-us/windows/always-connected-laptop-pcs|title=Always Connected PCs, Extended Battery Life 4G LTE Laptops {{!}} Windows|website=www.microsoft.com|language=en-us|access-date=2018-10-06}}</ref>
* [[MediaTek]], typically based on ARM
** [[List of MediaTek systems on chips|Dimensity]] & Kompanio Series. Standalone application & tablet processors that power devices such as Amazon Echo Show

=== Personal computers ===
In 1992, [[Acorn Computers]] produced the [[Acorn Archimedes#New range and a laptop|A3010, A3020 and A4000 range of personal computers]] with the ARM250 SoC. It combined the original Acorn ARM2 processor with a memory controller (MEMC), video controller (VIDC), and I/O controller (IOC). In previous Acorn [[ARM architecture|ARM]]-powered computers, these were four discrete chips. The ARM7500 chip was their second-generation SoC, based on the ARM700, VIDC20 and IOMD controllers, and was widely licensed in embedded devices such as set-top-boxes, as well as later Acorn personal computers.

Tablet and laptop manufacturers have learned lessons from embedded systems and smartphone markets about reduced power consumption, better performance and reliability from tighter [[System integration|integration]] of hardware and [[firmware]] [[Module system|modules]], and [[LTE (telecommunication)|LTE]] and other [[wireless network]] communications integrated on chip (integrated [[network interface controller]]s).<ref>{{Cite news|url=https://www.qualcomm.com/products/modems|title=Gigabit Class LTE, 4G LTE and 5G Cellular Modems {{!}} Qualcomm|work=Qualcomm|access-date=2018-10-13|language=en}}</ref>

On modern laptops and mini PCs, the low-power variants of [[AMD Ryzen]] and [[Intel Core]] processors use SoC design integrating CPU, IGPU, chipset and other processors in a single package. However, such x86 processors still require external memory and storage chips.

== Structure ==
An SoC consists of hardware [[functional unit]]s, including [[microprocessor]]s that run [[Computer program|software code]], as well as a [[communications subsystem]] to connect, control, direct and interface between these functional modules.

=== Functional components ===
==== Processor cores ====
An SoC must have at least one [[processor core]], but typically an SoC has more than one core. Processor cores can be a [[microcontroller]], [[microprocessor]] (μP),<ref name="Furber ARM">{{Cite book|title=ARM system-on-chip architecture|last=Furber|first=Stephen B.|publisher=Addison-Wesley|year=2000|isbn=0-201-67519-6|location=Harlow, England|oclc=44267964}}</ref> [[digital signal processor]] (DSP) or [[application-specific instruction set processor]] (ASIP) core.<ref name=":1">{{Cite book|title=Pipelined Multiprocessor System-on-Chip for Multimedia|publisher=[[Springer-Verlag|Springer]]|year=2014|isbn=978-3-319-01113-4|oclc=869378184|author=Haris Javaid |author2=Sri Parameswaran }}</ref> ASIPs have [[Instruction set architecture|instruction sets]] that are customized for an [[application domain]] and designed to be more efficient than general-purpose instructions for a specific type of workload. Multiprocessor SoCs have more than one processor core by definition. The [[ARM architecture]] is a common choice for SoC processor cores because some ARM-architecture cores are [[Soft microprocessor|soft processor]]s specified as [[IP core]]s.<ref name="Furber ARM" />

==== Memory ====
{{Further|Computer memory}}
SoCs must have [[semiconductor memory]] blocks to perform their computation, as do [[microcontroller]]s and other [[embedded system]]s. Depending on the application, SoC memory may form a [[memory hierarchy]] and [[cache hierarchy]]. In the mobile computing market, this is common, but in many [[Low-power electronics|low-power]] embedded microcontrollers, this is not necessary. Memory technologies for SoCs include [[read-only memory]] (ROM), [[random-access memory]] (RAM), Electrically Erasable Programmable ROM ([[EEPROM]]) and [[flash memory]].<ref name="Furber ARM" /> As in other computer systems, RAM can be subdivided into relatively faster but more expensive [[Static random-access memory|static RAM]] (SRAM) and the slower but cheaper [[Dynamic random-access memory|dynamic RAM]] (DRAM). When an SoC has a [[Cache (computing)|cache]] hierarchy, SRAM will usually be used to implement [[processor register]]s and cores' [[CPU cache|built-in cache]]s whereas DRAM will be used for [[main memory]]. "Main memory" may be specific to a single processor (which can be [[Multi-core processor|multi-core]]) when the SoC [[Multi-processor system-on-chip|has multiple processors]], in this case it is [[distributed memory]] and must be sent via {{Section link||Intermodule communication|nopage=y}} on-chip to be accessed by a different processor.<ref name=":1" /> For further discussion of multi-processing memory issues, see [[cache coherence]] and [[memory latency]].

==== Interfaces ====
SoCs include external [[Electrical connector|interfaces]], typically for [[communication protocol]]s. These are often based upon industry standards such as [[USB]], [[Ethernet]], [[Universal synchronous and asynchronous receiver-transmitter|USART]], [[Serial Peripheral Interface|SPI]], [[HDMI]], [[I²C]], [[Camera Serial Interface|CSI]], etc. These interfaces will differ according to the intended application. [[Wireless network]]ing protocols such as [[Wi-Fi]], [[Bluetooth]], [[6LoWPAN]] and [[near-field communication]] may also be supported.

When needed, SoCs include [[Analog signal|analog]] interfaces including [[Analog-to-digital converter|analog-to-digital]] and [[digital-to-analog converter]]s, often for [[signal processing]]. These may be able to interface with different types of [[sensor]]s or [[actuator]]s, including [[smart transducer]]s. They may interface with application-specific [[modularity|modules]] or shields.<ref group="nb">In [[embedded system]]s, "shields" are analogous to [[expansion card]]s for [[Personal computer|PCs]]. They often fit over a [[microcontroller]] such as an [[Arduino]] or [[single-board computer]] such as the [[Raspberry Pi]] and function as [[peripheral]]s for the device.</ref> Or they may be internal to the SoC, such as if an analog sensor is built in to the SoC and its readings must be converted to digital signals for mathematical processing.

==== Digital signal processors ====
[[Digital signal processor]] (DSP) cores are often included on SoCs. They perform [[signal processing]] operations in SoCs for [[sensor]]s, [[actuator]]s, [[data collection]], [[data analysis]] and multimedia processing. DSP cores typically feature [[very long instruction word]] (VLIW) and [[single instruction, multiple data]] (SIMD) [[instruction set architecture]]s, and are therefore highly amenable to exploiting [[instruction-level parallelism]] through [[Parallel processing (DSP implementation)|parallel processing]] and [[superscalar execution]].<ref name=":1" />{{Rp|4}}  SP cores most often feature application-specific instructions, and as such are typically [[application-specific instruction set processor]]s (ASIP). Such application-specific instructions correspond to dedicated hardware [[functional unit]]s that compute those instructions.

Typical DSP instructions include [[Multiply–accumulate operation|multiply-accumulate]], [[Fast Fourier transform]], [[Fused multiply-accumulate|fused multiply-add]], and [[convolution]]s.

==== Other ====
As with other computer systems, SoCs require [[Clock generator|timing sources]] to generate [[clock signal]]s, control execution of SoC functions and provide time context to [[signal processing]] applications of the SoC, if needed. Popular time sources are [[crystal oscillators]] and [[phase-locked loop]]s.

SoC [[peripheral]]s including [[counter (digital)|counter]]-timers, real-time [[timer]]s and [[power-on reset]] generators. SoCs also include [[voltage regulator]]s and [[power management]] circuits.

=== Intermodule communication ===
SoCs comprise many [[execution unit]]s. These units must often send data and [[Instruction (computing)|instructions]] back and forth. Because of this, all but the most trivial SoCs require [[Communications system|communications subsystems]]. Originally, as with other [[microcomputer]] technologies, [[Bus (computing)|data bus]] architectures were used, but recently designs based on sparse intercommunication networks known as [[Network on a chip|networks-on-chip]] (NoC) have risen to prominence and are forecast to overtake bus architectures for SoC design in the near future.<ref name=":0">{{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last1=Kundu|first1=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=978-1-4665-6527-2|edition=1st|location=Boca Raton, FL|oclc=895661009}}</ref>

==== Bus-based communication ====
Historically, a shared global [[bus (computing)|computer bus]] typically connected the different components, also called "blocks" of the SoC.<ref name=":0" /> A very common bus for SoC communications is ARM's royalty-free Advanced Microcontroller Bus Architecture ([[Advanced Microcontroller Bus Architecture|AMBA]]) standard.

[[Direct memory access]] controllers route data directly between external interfaces and SoC memory, bypassing the CPU or [[control unit]], thereby increasing the data [[throughput]] of the SoC. This is similar to some [[device driver]]s of peripherals on component-based [[multi-chip module]] PC architectures.

Wire delay is not scalable due to continued [[miniaturization]], [[Computer performance|system performance]] does not scale with the number of cores attached, the SoC's [[operating frequency]] must decrease with each additional core attached for power to be sustainable, and long wires consume large amounts of electrical power. These challenges are prohibitive to supporting [[Manycore processor|manycore]] systems on chip.<ref name=":0" />{{Rp|xiii}}

==== Network on a chip ====
{{Main|Network on a chip}}
In the late 2010s, a trend of SoCs implementing [[communications subsystem]]s in terms of a network-like topology instead of [[bus (computing)|bus-based]] protocols has emerged. A trend towards more processor cores on SoCs has caused on-chip communication efficiency to become one of the key factors in determining the overall system performance and cost.<ref name=":0" />{{Rp|xiii}} This has led to the emergence of interconnection networks with [[Router (computing)|router]]-based [[packet switching]] known as "[[network on a chip|networks on chip]]" (NoCs) to overcome the [[Bottleneck (engineering)|bottlenecks]] of bus-based networks.<ref name=":0" />{{Rp|xiii}}

Networks-on-chip have advantages including destination- and application-specific [[routing]], greater power efficiency and reduced possibility of [[bus contention]]. Network-on-chip architectures take inspiration from [[communication protocols]] like [[Transmission Control Protocol|TCP]] and the [[Internet protocol suite]] for on-chip communication,<ref name=":0" /> although they typically have fewer [[network layer]]s. Optimal network-on-chip [[network architecture]]s are an ongoing area of much research interest. NoC architectures range from traditional distributed computing [[Network topology|network topologies]] such as [[Torus interconnect|torus]], [[Hypercube internetwork topology|hypercube]], [[Mesh networking|meshes]] and [[tree network]]s to [[genetic algorithm scheduling]] to [[randomized algorithm]]s such as [[Branching random walk|random walks with branching]] and randomized [[time to live]] (TTL).

Many SoC researchers consider NoC architectures to be the future of SoC design because they have been shown to efficiently meet power and throughput needs of SoC designs. Current NoC architectures are two-dimensional. 2D IC design has limited [[Floorplan (microelectronics)|floorplanning]] choices as the number of cores in SoCs increase, so as [[three-dimensional integrated circuit]]s (3DICs) emerge, SoC designers are looking towards building three-dimensional on-chip networks known as 3DNoCs.<ref name=":0" />

== Design flow ==
{{More citations needed section|date=March 2017}}
{{Main|Design flow (EDA)|Physical design (electronics)|Platform-based design|l1=Electronics design flow|l3=}}{{See also|Systems design|Software design|label 2=Software design process}}
[[File:SoCDesignFlow.svg|upright=1.3|thumb|SoC design flow]]

A system on a chip consists of both the [[electronic hardware|hardware]], described in {{Section link||Structure|nopage=y}}, and the software controlling the microcontroller, microprocessor or digital signal processor cores, peripherals and interfaces. The [[design flow (EDA)|design flow]] for an SoC aims to develop this hardware and software at the same time, also known as architectural co-design. The design flow must also take into account optimizations ({{Section link||Optimization goals|nopage=y}}) and constraints.

Most SoCs are developed from pre-qualified hardware component [[Semiconductor intellectual property core|IP core specifications]] for the hardware elements and [[execution unit]]s, collectively "blocks", described above, together with software [[device driver]]s that may control their operation. Of particular importance are the [[protocol stack]]s that drive industry-standard interfaces like [[Universal Serial Bus|USB]].  The hardware blocks are put together using [[computer-aided design]] tools, specifically [[electronic design automation]] tools; the [[modular programming|software modules]] are integrated using a software [[integrated development environment]].

SoCs components are also often designed in [[high-level programming language]]s such as [[C++]], [[MATLAB]] or [[SystemC]] and converted to [[Register-transfer level|RTL]] designs through [[high-level synthesis]] (HLS) tools such as [[C to HDL]] or [[flow to HDL]].<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=August 25, 2011|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> HLS products called "algorithmic synthesis" allow designers to use C++ to model and synthesize system, circuit, software and verification levels all in one high level language commonly known to [[computer engineers]] in a manner independent of time scales, which are typically specified in HDL.<ref>{{Cite web|url=https://www.eetimes.com/document.asp?doc_id=1271261|title=The 'why' and 'what' of algorithmic synthesis|last=Bowyer|first=Bryan|date=February 5, 2005|website=[[EE Times]]|access-date=2018-10-08}}</ref> Other components can remain software and be compiled and embedded onto [[Soft microprocessor|soft-core processors]] included in the SoC as modules in HDL as [[Semiconductor intellectual property core|IP cores]].

Once the [[Computer architecture|architecture]] of the SoC has been defined, any new hardware elements are written in an abstract [[hardware description language]] termed [[Register-transfer level|register transfer level]] (RTL) which defines the circuit behavior, or synthesized into RTL from a high level language through high-level synthesis. These elements are connected together in a hardware description language to create the full SoC design. The logic specified to connect these components and convert between possibly different interfaces provided by different vendors is called [[glue logic]].

=== Design verification ===
{{Further|Functional verification|Signoff (electronic design automation)||label2=}}
Chips are verified for validation correctness before being sent to a [[Semiconductor fabrication plant|semiconductor foundry]]. This process is called [[functional verification]] and it accounts for a significant portion of the time and energy expended in the [[Integrated circuit development|chip design life cycle]], often quoted as 70%.<ref name="70% verification?">[[EE Times]]. "[http://www.eetimes.com/author.asp?section_id=36&doc_id=1264922 Is verification really 70 percent?]." June 14, 2004. Retrieved July 28, 2015.</ref><ref name="verification vs. validation">{{cite web|url=http://www.softwaretestingclass.com/difference-between-verification-and-validation/|title=Difference between Verification and Validation|work=Software Testing Class|date=August 26, 2013|access-date=2018-04-30|quote=In interviews most of the interviewers are asking questions on "What is Difference between Verification and Validation?" Many people use verification and validation interchangeably but both have different meanings.}}</ref> With the growing complexity of chips, [[hardware verification language]]s like [[SystemVerilog]], [[SystemC]], [[e (verification language)|e]], and OpenVera are being used. [[Software bug|Bugs]] found in the verification stage are reported to the designer.

Traditionally, engineers have employed simulation acceleration, [[emulator|emulation]] or prototyping on [[Reconfigurable computing|reprogrammable hardware]] to verify and debug hardware and software for SoC designs prior to the finalization of the design, known as [[tape-out]]. [[Field-programmable gate array]]s (FPGAs) are favored for prototyping SoCs because [[FPGA prototyping|FPGA prototypes]] are reprogrammable, allow [[debugging]] and are more flexible than [[application-specific integrated circuit]]s (ASICs).<ref name="nm prototyping">{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=January 5, 2006|website=Tayden Design|access-date=2018-10-07}}</ref><ref name="Reason to debug in FPGA">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref>

With high capacity and fast compilation time, simulation acceleration and emulation are powerful technologies that provide wide visibility into systems. Both technologies, however, operate slowly, on the order of MHz, which may be significantly slower – up to 100 times slower – than the SoC's operating frequency. Acceleration and emulation boxes are also very large and expensive at over US$1&nbsp;million.{{Citation needed|date=May 2018}}

FPGA prototypes, in contrast, use FPGAs directly to enable engineers to validate and test at, or close to, a system's full operating frequency with real-world stimuli. Tools such as Certus<ref>Brian Bailey, EE Times. "[http://www.eetimes.com/document.asp?doc_id=1317504 Tektronix hopes to shake up ASIC prototyping]." October 30, 2012. Retrieved July 28, 2015.</ref> are used to insert probes in the FPGA RTL that make signals available for observation. This is used to debug hardware, firmware and software interactions across multiple FPGAs with capabilities similar to a logic analyzer.

In parallel, the hardware elements are grouped and passed through a process of [[logic synthesis]], during which performance constraints, such as operational frequency and expected signal delays, are applied. This generates an output known as a [[netlist]] describing the design as a physical circuit and its interconnections. These netlists are combined with the [[glue logic]] connecting the components to produce the schematic description of the SoC as a circuit which can be [[printed circuit board|printed]] onto a chip. This process is known as [[place and route]] and precedes [[tape-out]] in the event that the SoCs are produced as [[application-specific integrated circuit]]s (ASIC).

== Optimization goals ==
SoCs must optimize [[Power consumption|power use]], area on [[Die (integrated circuit)|die]], communication, positioning for [[Locality of reference|locality]] between modular units and other factors. Optimization is necessarily a design goal of SoCs. If optimization was not necessary, the engineers would use a [[multi-chip module]] architecture without accounting for the area use, power consumption or performance of the system to the same extent.

Common optimization targets for SoC designs follow, with explanations of each. In general, optimizing any of these quantities may be a hard [[combinatorial optimization]] problem, and can indeed be [[NP-hardness|NP-hard]] fairly easily. Therefore, sophisticated [[optimization algorithm]]s are often required and it may be practical to use [[approximation algorithm]]s or [[Heuristic (computer science)|heuristics]] in some cases. Additionally, most SoC designs contain [[Multivariate optimization|multiple variables to optimize simultaneously]], so [[Pareto efficiency|Pareto efficient]] solutions are sought after in SoC design. Oftentimes the goals of optimizing some of these quantities are directly at odds, further adding complexity to design optimization of SoCs and introducing [[Trade-off#Engineering|trade-offs]] in system design.

For broader coverage of trade-offs and [[requirements analysis]], see [[requirements engineering]].

=== Targets ===
==== Power consumption ====
SoCs are optimized to minimize the [[Electric power#Definition|electrical power]] used to perform the SoC's functions. Most SoCs must use low power. SoC systems often require long [[battery life]] (such as [[smartphone]]s), can potentially spend months or years without a power source while needing to maintain autonomous function, and often are limited in power use by a high number of [[Embedded system|embedded]] SoCs being [[Distributed computing|networked together]] in an area. Additionally, energy costs can be high and conserving energy will reduce the [[total cost of ownership]] of the SoC. Finally, [[waste heat]] from high energy consumption can damage other circuit components if too much heat is dissipated, giving another pragmatic reason to conserve energy. The amount of energy used in a circuit is the [[integral]] of [[Power (physics)|power]] consumed with respect to time, and the [[Mean value theorem|average rate]] of power consumption is the product of [[Electric current|current]] by [[voltage]]. Equivalently, by [[Ohm's law]], power is current squared times resistance or voltage squared divided by [[Resistance (physics)|resistance]]:

<math display="block">P = IV = \frac{V^2}{R} = {I^2}{R}</math>SoCs are frequently embedded in [[Mobile device|portable devices]] such as [[smartphones]], [[GPS navigation device]]s, digital [[Digital watch|watches]] (including [[smartwatch]]es) and [[netbook]]s. Customers want long battery lives for [[mobile computing]] devices, another reason that power consumption must be minimized in SoCs. [[Multimedia application]]s are often executed on these devices, including video games, [[video streaming]], [[image processing]]; all of which have grown in [[computational complexity]] in recent years with user demands and expectations for higher-[[Video quality|quality]] multimedia. Computation is more demanding as expectations move towards [[3D video]] at [[high resolution]] with [[List of video compression formats|multiple standards]], so SoCs performing multimedia tasks must be computationally capable platform while being low power to run off a standard mobile battery.<ref name=":1" />{{Rp|3}}

==== Performance per watt ====
{{See also|Green computing}}
SoCs are optimized to maximize [[power efficiency]] in performance per watt: maximize the performance of the SoC given a budget of power usage. Many applications such as [[edge computing]], [[distributed processing]] and [[ambient intelligence]] require a certain level of [[Computer performance|computational performance]], but power is limited in most SoC environments. 

==== Waste heat ====
{{Main|Heat generation in integrated circuits}}{{See also|Thermal management (electronics)|Thermal design power|label 1=Thermal management in electronics}}
SoC designs are optimized to minimize [[waste heat]] [[dissipation|output]] on the chip. As with other [[integrated circuit]]s, heat generated due to high [[power density]] are the [[Bottleneck (engineering)|bottleneck]] to further [[miniaturization]] of components.<ref name=":2">{{Cite book|title=Heat Management in Integrated circuits: On-chip and system-level monitoring and cooling|last=Ogrenci-Memik|first=Seda|publisher=The Institution of Engineering and Technology|year=2015|isbn=978-1-84919-935-3|location=London, United Kingdom|oclc=934678500}}</ref>{{Rp|1}} The power densities of high speed integrated circuits, particularly microprocessors and including SoCs, have become highly uneven. Too much waste heat can damage circuits and erode [[Reliability (semiconductor)|reliability]] of the circuit over time. High temperatures and thermal stress negatively impact reliability, [[stress migration]], decreased [[mean time between failures]], [[electromigration]], [[wire bonding]], [[Metastability (electronics)|metastability]] and other performance degradation of the SoC over time.<ref name=":2" />{{Rp|2–9}}

In particular, most SoCs are in a small physical area or volume and therefore the effects of waste heat are compounded because there is little room for it to diffuse out of the system. Because of high [[transistor count]]s on modern devices, oftentimes a layout of sufficient throughput and high [[Transistors density|transistor density]] is physically realizable from [[Semiconductor device fabrication|fabrication processes]] but would result in unacceptably high amounts of heat in the circuit's volume.<ref name=":2" />{{Rp|1}}

These thermal effects force SoC and other chip designers to apply conservative [[design margin]]s, creating less performant devices to mitigate the risk of [[catastrophic failure]]. Due to increased [[Transistors density|transistor densities]] as length scales get smaller, each [[Semiconductor node|process generation]] produces more heat output than the last. Compounding this problem, SoC architectures are usually heterogeneous, creating spatially inhomogeneous [[heat flux]]es, which cannot be effectively mitigated by uniform [[passive cooling]].<ref name=":2" />{{Rp|1}}

==== Throughput ====
{{Expand section|date=October 2018}}
SoCs are optimized to maximize computational and communications [[throughput]].

==== Latency ====
{{Expand section|date=October 2018}}
SoCs are optimized to minimize [[Latency (engineering)|latency]] for some or all of their functions. This can be accomplished by [[Integrated circuit layout|laying out]] elements with proper proximity and [[Locality of reference|locality]] to each-other to minimize the interconnection delays and maximize the speed at which data is communicated between modules, [[Execution unit|functional units]] and memories. In general, optimizing to minimize latency is an [[NP-completeness|NP-complete]] problem equivalent to the [[Boolean satisfiability problem]].

For [[Task (computing)|tasks]] running on processor cores, latency and throughput can be improved with [[Scheduling (computing)|task scheduling]]. Some tasks run in application-specific hardware units, however, and even task scheduling may not be sufficient to optimize all software-based tasks to meet timing and throughput constraints.

=== Methodologies ===
{{Further|Multi-objective optimization|Multiple-criteria decision analysis|Architecture tradeoff analysis method|label3=Architecture tradeoff analysis}}
{{Expand section|date=October 2018|small=no}}
Systems on chip are modeled with standard hardware [[verification and validation]] techniques, but additional techniques are used to model and optimize SoC design alternatives to make the system optimal with respect to [[multiple-criteria decision analysis]] on the above optimization targets.

==== Task scheduling ====
[[Scheduling (computing)|Task scheduling]] is an important activity in any computer system with multiple [[Process (computing)|processes]] or [[Thread (computing)|threads]] sharing a single processor core. It is important to reduce {{Section link||Latency|nopage=y}} and increase {{Section link||Throughput|nopage=y}} for [[embedded software]] running on an SoC's {{Section link||Processor cores|nopage=y}}.  Not every important computing activity in a SoC is performed in software running on on-chip processors, but scheduling can drastically improve performance of software-based tasks and other tasks involving [[shared resource]]s.

Software running on SoCs often schedules tasks according to [[network scheduling]] and [[Stochastic scheduling|randomized scheduling]] algorithms.

==== Pipelining ====
{{Broader|Pipeline (computing)}}
Hardware and software tasks are often pipelined in [[processor design]]. Pipelining is an important principle for [[speedup]] in [[computer architecture]]. They are frequently used in [[GPU]]s ([[graphics pipeline]]) and RISC processors (evolutions of the [[classic RISC pipeline]]), but are also applied to application-specific tasks such as [[digital signal processing]] and multimedia manipulations in the context of SoCs.<ref name=":1" />

==== Probabilistic modeling ====
SoCs are often analyzed though [[probabilistic model]]s, [[Queueing theory#Queueing networks|queueing network]]s, and [[Markov chain]]s. For instance, [[Little's law]] allows SoC states and NoC buffers to be modeled as arrival processes and analyzed through [[Poisson random variable]]s and [[Poisson process]]es.

==== Markov chains ====
SoCs are often modeled with [[Markov chain]]s, both [[Markov chain#Discrete-time Markov chain|discrete time]] and [[Markov chain#Continuous-time Markov chain|continuous time]] variants. Markov chain modeling allows [[asymptotic analysis]] of the SoC's [[Markov chain#Steady-state analysis and limiting distributions|steady state distribution]] of power, heat, latency and other factors to allow design decisions to be optimized for the common case.

== Fabrication ==
{{More citations needed section|date=March 2017}}{{See|Semiconductor device fabrication}}

SoC chips are typically [[semiconductor device fabrication|fabricated]] using [[metal–oxide–semiconductor]] (MOS) technology.<ref>{{cite book |last1=Lin |first1=Youn-Long Steve |title=Essential Issues in SOC Design: Designing Complex Systems-on-Chip |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=978-1-4020-5352-8 |page=176 |url=https://books.google.com/books?id=7OV9lEn9LiQC&pg=PA176}}</ref> The netlists described above are used as the basis for the physical design ([[place and route]]) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.

When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.

SoCs can be fabricated by several technologies, including:
* [[Full custom]] [[ASIC]]
* [[Standard cell]] ASIC
* [[Field-programmable gate array]] (FPGA)

ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=July 17, 2018 |language=en-US|access-date=2018-10-17}}</ref>

SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.

However, like most [[very-large-scale integration]] (VLSI) designs, the total cost{{Clarify|reason=what kind of cost?|date=May 2018}} is higher for one large chip than for the same functionality distributed over several smaller chips, because of [[Semiconductor device fabrication#Device test|lower yields]]{{Clarify|reason=confusing to non-experts|date=May 2018}} and higher [[non-recurring engineering]] costs.

When it is not feasible to construct an SoC for a particular application, an alternative is a [[system in package]] (SiP) comprising a number of chips in a single [[chip carrier|package]]. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.<ref>[[EE Times]]. "[http://www.eetimes.com/document.asp?doc_id=1153043 The Great Debate: SOC vs. SIP]." March 21, 2005. Retrieved July 28, 2015.</ref> Another reason SiP may be preferred is [[waste heat]] may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.

==Examples==
Some examples of systems on a chip are:

*[[Apple A series]]
*[[Cell (processor)|Cell processor]]
*[[Adapteva]]'s Epiphany architecture
*[[Xilinx]] Zynq UltraScale
*[[Qualcomm Snapdragon]]

== Benchmarks ==
{{Expand section|date=October 2018}}
SoC [[research and development]] often compares many options. Benchmarks, such as COSMIC,<ref>{{Cite web|url=http://www.ece.ust.hk/~eexu/COSMIC.html|title=COSMIC|website=www.ece.ust.hk|access-date=2018-10-08}}</ref> are developed to help such evaluations.

== See also ==
* [[Chiplet]]
* [[List of system on a chip suppliers]]
* [[Post-silicon validation]]
* [[ARM architecture family]]
* [[RISC-V]]
* [[Single-board computer]]
* [[System in a package]]
* [[Network on a chip]]
* [[Cypress PSoC]]
* [[Application-specific instruction set processor]] (ASIP)
* [[Platform-based design]]
* [[Lab-on-a-chip]]
* [[Organ-on-a-chip]] in biomedical technology
* [[Multi-chip module]]
* [[Parallel computing]]
* [[ARM big.LITTLE]] co-architecture
* [[Hardware acceleration]]

== Notes ==
{{reflist|group=nb}}

== References ==
{{reflist}}

== Further reading ==
* {{cite book |editor1-first=Wael |editor1-last=Badawy |editor2-first=Graham A. |editor2-last=Jullien |year=2003 |title=System-on-Chip for Real-Time Applications |series=Kluwer international series in engineering and computer science, SECS 711 |publisher=[[Wolters Kluwer|Kluwer Academic Publishers]] |location=Boston |isbn=978-1-4020-7254-3 |oclc=50478525 |url=https://books.google.com/books?id=Ha76NqrqPVIC}} 465 pages.
* {{cite book |author=Furber, Stephen B. |title=ARM system-on-chip architecture |publisher=Addison-Wesley |location=Boston |year=2000 |isbn=0-201-67519-6 |title-link=ARM system-on-chip architecture }}
* {{Cite book|title=Network-on-chip: the Next Generation of System-on-Chip Integration|last1=Kundu|first1=Santanu|last2=Chattopadhyay|first2=Santanu|publisher=CRC Press|year=2014|isbn=978-1-4665-6527-2|edition=1st|location=Boca Raton, FL|oclc=895661009}}

== External links ==
<!-- Follow [[WP:EL]] guidelines before adding anything to this section -->
* [http://www.ieee-socc.org/ SOCC] Annual [[Institute of Electrical and Electronics Engineers|IEEE]] International SoC Conference
* [http://www.edautils.com/Baya.html Baya] free SoC platform assembly and IP integration tool
*[http://www.eng.auburn.edu/~nelson/courses/elec5260_6260/Systems%20on%20Chip%20(SoC).pdf Systems on Chip for Embedded Applications], [[Auburn University]] seminar in [[Very-large-scale integration|VLSI]]
* [http://www.fpga-cores.com/instant-soc/ Instant SoC] SoC for FPGAs defined by C++
* [https://web.archive.org/web/20130614083645/http://mpsoc-forum.org/ MPSoC – Annual Conference on MPSoC]
* [https://web.archive.org/web/20090215035428/http://www.u-aizu.ac.jp/~benab/conferences/mcsoc-09/ Annual Symposium]

{{Systems on chip}}{{CPU technologies}}
{{Single-board computer}}
{{Programmable Logic}}
{{Computer science}}
{{Hardware acceleration}}

[[Category:System on a chip| ]]
[[Category:Computer engineering]]
[[Category:Electronic design]]
[[Category:Microtechnology]]
[[Category:Hardware acceleration]]
[[Category:Computer systems]]
[[Category:Application-specific integrated circuits]]