View source for IMPLY gate

{{Short description|Digital logic gate}}
{{noref|date=August 2020}}
{| class="wikitable" style="float:right;"
|-  style="background:#def; text-align:center;"
|colspan=2|'''Input'''<br>A &nbsp; B || '''Output'''<br> A → B
|- 
|{{no2|0}} || {{no2|0}} || {{yes2|1}}
|- 
|{{no2|0}} || {{yes2|1}} || {{yes2|1}}
|- 
|{{yes2|1}} || {{no2|0}} || {{no2|0}}
|-
|{{yes2|1}} || {{yes2|1}} || {{yes2|1}}
|}

The '''IMPLY gate''' is an informal digital [[logic gate]] that implements a [[logical conditional]]. 

==Symbols==
IMPLY can be denoted in algebraic expressions with the [[List of logic symbols|logic symbol]] right-facing arrow (→). Logically, it is equivalent to [[Material_conditional|material implication]], and the logical expression ¬A v B.

There are two symbols for IMPLY gates: the traditional symbol and the [[Institute of Electrical and Electronics Engineers|IEEE]] symbol. For more information see [[Logic gate#Symbols|Logic gate symbols]].

{|  style="margin:auto; text-align:center;"
|-
|[[Image:IMPLY ANSI.svg]]
|
|[[Image:IEC Implies gate.svg]]
|-
|''Traditional IMPLY Symbol''
|
|''IEEE IMPLY Symbol''
|}
{{Clear}}
==Functional completeness==
While the Implication gate isn't [[Functional completeness|functionally complete]] by itself, it is in conjunction with the constant 0 source. This can be shown via the following: 

<math>\begin{align}
  A \rightarrow 0 &:= \neg A \\
  (A \rightarrow 0) \rightarrow B &= \neg (\neg A) \lor B \\
  &= A \lor B.
\end{align}</math>

Thus as the implication gate with the addition of the constant 0 source can create both the NOT gate and the OR gate, it can create the NOR gate, which is a universal gate. 
==See also==
{{Commons category|IMPLY_gates}}
*[[NIMPLY gate]]
*[[AND gate]]
*[[Inverter (logic gate)|NOT gate]]
*[[NAND gate]]
*[[NOR gate]]
*[[XOR gate]]
*[[XNOR gate]]
*[[Boolean algebra (logic)]]
*[[Logic gates]]
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==References==
{{reflist}}-->

{{Logical connectives}}

[[Category:Logic gates]]


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