View source for Differential signalling

{{Short description|Method for electrically transmitting information}}
{{About|electric signals via wires|an immunology concept|Differential signalling hypothesis}}
{{Refimprove|date=January 2021}}
{{Use British English|date=May 2021}}
{{Use dmy dates|date=February 2022|cs1-dates=y}}
{{Use list-defined references|date=February 2022}}

[[Image:Differential signal transmission.svg|thumb|upright=1.5|A signal transmitted differentially. Notice the increased amplitude at the receiving end.]]

'''Differential signalling''' is a method for [[electrically]] transmitting [[information]] using two complementary [[signal]]s. The technique sends the same electrical signal as a '''differential pair''' of signals, each in its own [[Electrical conductor|conductor]]. The pair of conductors can be wires in a [[twisted-pair]] or [[ribbon cable]] or traces on a [[printed circuit board]]. 

Electrically, the two conductors carry [[voltage]] signals which are equal in [[Absolute value|magnitude]], but of opposite [[Electrical polarity|polarity]]. The receiving circuit responds to the difference between the two signals, which results in a signal with a magnitude twice as large.

The [[symmetrical]] signals of differential signalling may be referred to as ''balanced'', but this term is more appropriately applied to [[balanced circuit]]s and [[balanced line]]s which reject [[common-mode interference]] when fed into a differential receiver. Differential signalling does not make a line balanced, nor does [[Noise (electronics)|noise]] rejection in balanced circuits require differential signalling. 

Differential signalling is to be contrasted to [[single-ended signalling]] which drives only one conductor with signal, while the other is connected to a fixed reference voltage.

==Advantages==
Contrary to popular belief, differential signalling does not affect noise cancellation. [[Balanced line]]s with differential receivers will reject noise regardless of whether the signal is differential or single-ended,<ref name="Blyth_2009"/><ref name="IEC_2001"/> but since balanced line noise rejection requires a differential receiver anyway, differential signalling is often used on balanced lines. Some of the benefits of differential signalling include:
* Doubled signal voltage between the differential pair (compared to a single-ended signal of the same [[nominal level]]), giving 6&nbsp;dB extra [[headroom (audio signal processing)|headroom]].<ref name="Blyth_2009"/>
* [[Common-mode signal|Common-mode]] noise between the two amps (e.g. from imperfect [[power supply rejection ratio|power supply rejection]]) is easily rejected by a differential receiver.
* Longer cable runs are possible due to this increased noise immunity and 6&nbsp;dB extra headroom.
* At higher frequencies, the output impedance of the output amplifier can change, resulting in a small imbalance. When driven in differential mode by two identical amplifiers, this impedance change will be the same for both lines, and thus cancelled out.<ref name="Blyth_2009"/>

Differential signalling works for both analog signalling, as in [[balanced audio]], and in digital signalling, as in [[RS-422]], [[RS-485]], [[Ethernet over twisted pair]], [[PCI Express]], [[DisplayPort]], [[HDMI]] and [[USB]].

=== Suitability for use with low-voltage electronics ===
[[Image:Differential signal fed into a differential amplifier.svg|thumb|upright=1.5|Differential amplifiers respond to differential signals by amplifying the difference between the voltages on the amplifier’s two inputs.]]
The [[electronics industry]], particularly in portable and mobile devices, continually strives to lower supply voltage to save power.{{citation needed|date=July 2018}} A low supply voltage, however, reduces noise immunity. Differential signalling helps to reduce these problems because, for a given supply voltage, it provides twice the noise immunity of a single-ended system.

To see why, consider a single-ended digital system with supply voltage <math>V_S</math>. The high logic level is <math>V_S\,</math> and the low logic level is 0 V. The difference between the two levels is therefore <math>V_S - 0\,\mathrm{V} = V_S</math>. Now consider a differential system with the same supply voltage. The voltage difference in the high state, where one wire is at <math>V_S\,</math> and the other at 0 V, is <math>V_S - 0\,\mathrm{V} = V_S</math>. The voltage difference in the low state, where the voltages on the wires are exchanged, is <math>0\,\mathrm{V} - V_S = -V_S</math>.  The difference between high and low logic levels is therefore <math>V_S - (-V_S) = 2V_S\,</math>. This is twice the difference of the single-ended system. If the voltage noise on one wire is uncorrelated to the noise on the other one, it takes twice as much noise to cause an error with the differential system as with the single-ended system. In other words, differential signalling doubles the noise immunity.{{citation needed|date=March 2016}}

== Comparison with single-ended signalling ==
In single-ended signalling, the transmitter generates a single voltage that the receiver compares with a fixed reference voltage, both relative to a common ground connection shared by both ends. In many instances, single-ended designs are not feasible. Another difficulty is the electromagnetic interference that can be generated by a single-ended signalling system that attempts to operate at high speed.{{citation needed|date=August 2018}}

== Relation to balanced interfaces ==
{{Main|Balanced circuit}}
When transmitting signals differentially between two pieces of equipment it is common to do so through a balanced interface. An ''interface'' is a subsystem containing three parts: a driver, a line, and a receiver. These three components complete a full circuit for a signal to travel through and the impedances of this circuit is what determines whether the interface as a whole is balanced or not:<ref name="AES_2015"/> "A balanced circuit is a two-conductor circuit in which both conductors and all circuits connected to them have the same impedance to ground and to all other conductors."<ref name="Ott_1988"/> Balanced interfaces were developed as a protection scheme against noise. In theory, it can reject any interference so long as it is common-mode (voltages that appear with equal magnitude and the same polarity in both conductors).<ref name="AES_2015"/>

There exists great confusion as to what constitutes a balanced interface and how it relates to differential signalling. In reality, they are two completely independent concepts: balanced interfacing concerns noise and interference rejection, while differential signalling only concerns headroom. The impedance balance of a circuit does not determine the signals it can carry and vice versa.<ref name="AES_2015"/>

== Uses of differential pairs ==
The technique minimizes electronic [[crosstalk]] and [[electromagnetic interference]], both [[noise (electronics)|noise]] emission and noise acceptance, and can achieve a constant or known [[characteristic impedance]], allowing [[impedance matching]] techniques important in a high-speed signal [[transmission line]] or high-quality balanced line and balanced circuit audio signal path.

Differential pairs include:

* [[Twisted-pair]] cables, [[shielded cable|shielded]] and unshielded
* [[Microstrip]] and [[stripline]] differential pair routing techniques on [[printed circuit board]]s

Differential pairs generally carry differential or semi-differential signals, such as high-speed digital serial interfaces including [[LVDS]] differential [[Emitter coupled logic|ECL]], [[Positive Referenced Emitter Coupled Logic|PECL]], [[LVPECL]], [[Hypertransport]], [[Ethernet over twisted pair]], [[serial digital interface]], [[RS-422]], [[RS-485]], [[USB]], [[Serial ATA]], [[TMDS]], [[FireWire]], and [[HDMI]], etc., or else high quality and/or high frequency analog signals (e.g. [[video signal]]s, balanced audio signals, etc.).

Differential signalling often uses length-matched wires or conductors which are used in high speed [[serial link]]s.<ref>{{cite book | url=https://books.google.com/books?id=BxptEAAAQBAJ | title=Modern Computer Architecture and Organization: Learn x86, ARM, and RISC-V architectures and the design of smartphones, PCS, and cloud servers | isbn=978-1-80323-823-4 | last1=Ledin | first1=Jim | last2=Farley | first2=Dave | date=4 May 2022 | publisher=Packt Publishing }}</ref>

=== Data rate examples ===
Data rates of some interfaces implemented with differential pairs include the following:

* [[Serial ATA]] &ndash; 1.5&nbsp;Gbit/s
* [[Hypertransport]] &ndash; 1.6&nbsp;Gbit/s
* [[Infiniband]] &ndash; 2.5&nbsp;Gbit/s
* [[PCI Express]] &ndash; 2.5&nbsp;Gbit/s
* [[Serial ATA#2.0|Serial ATA Revision 2.0]] &ndash; 2.4&nbsp;Gbit/s
* [[XAUI]] &ndash; 3.125&nbsp;Gbit/s
* [[Serial ATA#3.0|Serial ATA Revision 3.0]] &ndash; 6&nbsp;Gbit/s
* [[PCI Express 2.0]] &ndash; 5.0&nbsp;Gbit/s per lane
* [[10 Gigabit Ethernet]] &ndash; 10&nbsp;Gbit/s (four differential pairs running at 2.5&nbsp;Gbit/s each)
* [[DDR SDRAM]] &ndash; 3.2&nbsp;Gbit/s (differential strobes latch single-ended data)

== Transmission lines ==
The type of [[transmission line]] that connects two devices (chips, modules) often dictates the type of signalling. Single-ended signalling is typically used with [[coaxial cable]]s, in which one conductor totally screens the other from the environment. All screens (or shields) are combined into a single piece of material to form a common ground. Differential signalling, however, is typically used with a balanced pair of conductors. For short cables and low frequencies, the two methods are equivalent, so cheap single-ended circuits with a common ground can be used with cheap cables. As signalling speeds become faster, wires begin to behave as transmission lines.

== Use in computers ==
Differential signalling is often used in computers to reduce [[electromagnetic interference]], because complete screening is not possible with [[microstrip]]s and [[microprocessor|chip]]s in computers, due to geometric constraints and the fact that screening does not work at DC. If a DC power supply line and a low-voltage signal line share the same ground, the power current returning through the ground can induce a significant voltage in it. A low-resistance ground reduces this problem to some extent. A balanced pair of microstrip lines is a convenient solution because it does not need an additional PCB layer, as a [[stripline]] does. Because each line causes a matching image current in the ground plane, which is required anyway for supplying power, the pair looks like four lines and therefore has a shorter crosstalk distance than a simple isolated pair. In fact, it behaves as well as a twisted pair. Low crosstalk is important when many lines are packed into a small space, as on a typical PCB.{{fact|date=January 2022}}

== {{anchor|HVD|HVDS}}High-voltage differential signalling ==
'''High-voltage differential (HVD) signalling''' uses high-[[voltage]] signals. In [[computer]] electronics, ''high voltage'' normally means 5 volts or more.

[[SCSI]]-1 variations included a high voltage differential (HVD) implementation whose maximum cable length was many times that of the single-ended version. SCSI equipment, for example, allows a maximum total cable length of 25 meters using HVD, while single-ended SCSI allows a maximum cable length of 1.5 to 6 meters, depending on bus speed. LVD versions of SCSI allow less than 25&nbsp;m cable length not because of the lower voltage, but because these SCSI standards allow much higher speeds than the older HVD SCSI.

The generic term ''high-voltage differential signalling'' describes a variety of systems. [[Low-voltage differential signalling]] (LVDS), on the other hand, is a specific system defined by a TIA/EIA standard.

== Polarity switching ==
{{anchor|Reversed polarity}}Some integrated circuits dealing with differential signals provide a hardware option (via [[strapping option]]s, under firmware control, or even automatic) to swap the polarity of the two differential signals, called ''differential pair swapping'', ''polarity reversion'', ''differential pair inversion'', ''polarity inversion'', or ''lane inversion''. This can be utilized to simplify or improve the [[routing (electronic design automation)|routing]] of high-speed differential pairs of traces on [[printed circuit board]]s in hardware development, to help to cope with common cabling errors through swapped wires, or easily fix common design errors under firmware control.<ref name="Intel_2012"/><ref name="Teledyne_2013"/><ref name="TI_2016"/><ref name="Altium_2020"/><ref name="Microchip_2020"/> {{anchor|Auto polarity}}Many [[Ethernet]] [[PHY]] [[transceiver]]s support this as ''auto polarity detection and correction'' (not to be confused with a similar ''[[auto crossover]]'' feature).<ref name="Micrel_2005"/> [[PCIe]] and [[USB SuperSpeed]] also support lane polarity inversion.

Another way to deal with polarity errors is to use [[Line_code#Polarity | polarity-insensitive line codes]].

==See also==
* [[Backplane]]s
* [[Common-mode signal]]
* [[Current loop]] signalling
* [[Current-mode logic]] (CML)
* [[DDR SDRAM]]
* [[Differential amplifier]]
* [[Differential TTL]]
* [[DisplayPort]]
* [[Humbucker]]
* [[Signal integrity]]
* [[Single-ended signaling]]
* [[Transition-minimized differential signaling]] (TMDS)

== References ==
{{Reflist|refs=
<ref name="AES_2015">{{cite book |author-first=Glenn M. |author-last=Ballou |title=Handbook for Sound Engineers |edition=Fifth |publisher=[[Taylor & Francis]] |date=2015 |pages=1267–1268}}</ref>
<ref name="Ott_1988">{{cite book |author-first=Henry W. |author-last=Ott |title=Noise Reduction Techniques in Electronic Systems |edition=Second |publisher=[[John Wiley & Sons]] |date=1988 |page=116}}</ref>
<ref name="Micrel_2005">{{cite web |title=New Generation Ethernet PHY with LinkMD |publisher=[[Micrel Incorporated]] / [[Microchip Technology]] |date=June 2005 |publication-place=San Jose, California, USA |id=Application Note 127, KS8001, M9999-060105, (408) 955-1690 |url=http://ww1.microchip.com/downloads/en/AppNotes/AN127-UNG.pdf |access-date=2022-02-25 }} (5 pages)</ref>
<ref name="Blyth_2009">{{cite web |title=Audio Balancing Issues |date=2009 |author-first=Graham |author-last=Blyth |author-link=Graham Blyth |work=White Papers |publisher=[[Soundcraft]] |url=http://www.soundcraft.com/support/fetchpalz.aspx?cat_id=white_papers&id=2 |access-date=2010-12-30 |url-status=dead |archive-url=https://web.archive.org/web/20100731162356/http://www.soundcraft.com/support/fetchpalz.aspx?cat_id=white_papers&id=2 |archive-date=2010-07-31 |quote=Let's be clear from the start here: if the source impedance of each of these signals was not identical i.e. balanced, the method would fail completely, the matching of the differential audio signals being irrelevant, though desirable for headroom considerations.}} (3 pages)</ref>
<ref name="IEC_2001">{{cite book |title=Sound system equipment |edition=Third |date=2000 |publisher=[[International Electrotechnical Commission]] |location=Geneva, Switzerland |id=IEC 602689-3:2001 |pages=111– |chapter=Part 3: Amplifiers |quote=Only the common-mode impedance balance of the driver, line, and receiver play a role in noise or interference rejection. This noise or interference rejection property is independent of the presence of a desired differential signal.}}</ref>
<ref name="Teledyne_2013">{{cite web |title=Understanding Lane Reversal and Polarity |date=2013-01-09 |publisher=[[Teledyne]] [[LeCroy]] |url=https://teledynelecroy.com/doc/understanding-lane-reversal-and-polarity |access-date=2022-02-25 |url-status=live |archive-url=https://web.archive.org/web/20210413083541/https://teledynelecroy.com/doc/understanding-lane-reversal-and-polarity |archive-date=2021-04-13}}</ref>
<ref name="Altium_2020">{{cite web |title=Simplify Routing With Pin, Part, And Diff-Pair Swapping |date=2020-10-27 |orig-date=2017-02-10 |publisher=Altium |work=White Papers |url=https://resources.altium.com/p/simplify-routing-with-pin-part-and-diff-pair-swapping |access-date=2022-02-25 |url-status=live |archive-url=https://web.archive.org/web/20210614221408/https://resources.altium.com/p/simplify-routing-with-pin-part-and-diff-pair-swapping |archive-date=2021-06-14}}</ref>
<ref name="TI_2016">{{cite web |title=TUSB73x0 Board Design and Layout Guidelines - User's Guide |date=February 2016 |orig-date=June 2011 |id=Literature Number: SLLU149E |publisher=[[Texas Instruments Incorporated]] |url=https://www.ti.com/lit/ug/sllu149e/sllu149e.pdf |access-date=2022-02-25 |url-status=live |archive-url=https://web.archive.org/web/20210506221758/http://www.ti.com/lit/ug/sllu149e/sllu149e.pdf |archive-date=2021-05-06}} (45 pages)</ref>
<ref name="Intel_2012">{{cite web |title=Can I swap the positive (p) and negative (n) signals of a differential pair? |id=ID: 000085787 |department=Troubleshooting |date=2012-09-11 |publisher=[[Intel]] |url=https://www.intel.com/content/www/us/en/support/programmable/articles/000085787.html |access-date=2022-02-25 |url-status=live |archive-url=https://web.archive.org/web/20220225065139/https://www.intel.com/content/www/sign-in.html?locale=us/en&TYPE=33554433&REALMOID=06-881bcb7e-6568-46ce-b682-efb1740f91e0&GUID=&SMAUTHREASON=0&METHOD=GET&SMAGENTNAME=$SM$E5%2f1NOwMxK6qjpdtcAD4nY4GArfTHEEMJCm5tOSlVtMEoanj%2bb2nCHI6hh8QBVNY&TARGET=$SM$https%3a%2f%2fsfederation%2eintel%2ecom%2ffederation2%2fsp%2fWebExperienceManagementSolutiononAEMforIntel%2fd3d3LmludGVsLmNvbQ$%3D$%3D |archive-date=2022-02-25}}</ref>
<ref name="Microchip_2020">{{cite web |title=Can the Ethernet transformer pairs be swapped |date=2020-03-03 |department=Knowledge |publisher=[[Microchip Technology]] |url=https://microchipsupport.force.com/s/article/Can-the-Ethernet-transformer-pairs-be-swapped |access-date=2022-02-25 |url-status=live |archive-url=https://web.archive.org/web/20200809093218/https://microchipsupport.force.com/s/article/Can-the-Ethernet-transformer-pairs-be-swapped |archive-date=2020-08-09}}</ref>
}}

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