View source for Bulldozer (microarchitecture)

{{short description|Microarchitecture by AMD}}
{{Use mdy dates|date=September 2024}}
{{Infobox CPU
| name           = Bulldozer - Family 15h
| image          = 
| image_size     = 138px
| caption        = 
| created        = {{Start date and age|October 12, 2011}}
| produced-start =
| size-from      = 32 nm
| manuf1         = [[AMD]]
| core1          = [[FX-4100|AMD FX]]
| core2          = [[Opteron#Opteron (32 nm SOI) – First Generation Bulldozer Microarchitecture|Opteron]]
| predecessor    = [[AMD 10h|Family 10h (K10)]]
| successor      = [[Piledriver (microarchitecture)|Piledriver - Family 15h (2nd-gen)]]
| sock1          = [[Socket AM3+]]
| arch           = [[X86-64#Microarchitecture_levels|x86-64-v2]]
}}

The '''AMD Bulldozer Family 15h''' is a [[microprocessor]] [[microarchitecture]] for the [[AMD FX|FX]] and [[Opteron]] line of processors, developed by [[Advanced Micro Devices|AMD]] for the desktop and server markets.<ref name=amd1>{{cite web|title=FX Processors|url=https://www.amd.com/en-gb/products/processors/desktop/fx#|website=AMD|access-date=24 February 2016|date=24 February 2016}}</ref><ref name=engadget1>{{cite web|title=AMD ships 16 core bulldozer powered Opteron 6200|url=https://www.engadget.com/2011/11/14/amd-ships-16-core-bulldozer-powered-opteron-6200/|website=Engadget|access-date=24 February 2016|date=14 November 2011}}</ref> Bulldozer is the [[codename]] for this family of microarchitectures. It was released on October 12, 2011, as the successor to the [[AMD 10h|K10]] microarchitecture.

Bulldozer is designed from scratch, not a development of earlier processors.<ref>{{citation|url=http://www.techpowerup.com/138328/Bulldozer-50-Faster-than-Core-i7-and-Phenom-II.html |title=Bulldozer 50% Faster than Core&nbsp;i7 and Phenom&nbsp;II |date=January 13, 2011 |publisher=techPowerUp |access-date=2012-01-23}}</ref> The core is specifically aimed at computing products with [[Thermal Design Power|TDP]]s of 10 to 125&nbsp;[[watt]]s. AMD claims dramatic performance-per-watt efficiency improvements in [[high-performance computing]] (HPC) applications with Bulldozer cores.

The ''Bulldozer'' cores support most of the instruction sets implemented by [[Intel]] processors ([[Sandy Bridge]]) available at its introduction (including [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], and [[Advanced Vector Extensions|AVX]]) as well as new instruction sets proposed by AMD; [[Bit Manipulation Instruction Sets|ABM]], [[XOP instruction set|XOP]], [[FMA4 instruction set|FMA4]] and [[F16C]].<ref>{{citation |url=http://support.amd.com/us/Embedded_TechDocs/43479.pdf |title=AMD64 Architecture Programmer's Manual Volume 6: 128-Bit and 256-Bit XOP, and FMA4 Instructions |date=May 1, 2009 |publisher=[[AMD]] |access-date=2009-05-08}}</ref><ref>{{citation |url=http://forums.amd.com/devblog/blogpost.cfm?threadid=112934&catid=208 |title=Striking a balance |date=7 May 2009 |publisher=Dave Christie, AMD Developer blogs |access-date=2009-05-08 |archive-date=2012-04-02 |archive-url=https://web.archive.org/web/20120402034956/http://blogs.amd.com/developer/ |url-status=dead }}</ref> Only Bulldozer GEN4 ([[Excavator (microarchitecture)|Excavator]]) supports [[AVX2]] instruction sets.

== Overview ==
According to AMD, Bulldozer-based CPUs are based on [[GlobalFoundries]]' 32&nbsp;nm [[Silicon on insulator|Silicon on insulator (SOI)]] process technology and reuses the approach of [[Digital Equipment Corporation|DEC]] for multitasking computer performance with the arguments that it, according to press notes, "balances dedicated and shared computer resources to provide a highly compact, high units count design that is easily replicated on a chip for performance scaling."<ref>{{citation |url=https://www.amd.com/us/press-releases/pages/amd-x86-innovation-new-core-designs-2010aug24.aspx |title=AMD Sets New Mark in x86 Innovation with First Detailed Disclosures of Two New Core Designs |publisher=[[AMD]] |date=August 24, 2011 |access-date=September 18, 2011 |page=1}}</ref> In other words, by eliminating some of the "redundant" elements that naturally creep into multicore designs, AMD has hoped to take better advantage of its hardware capabilities, while using less power.

Bulldozer-based implementations built on [[32 nanometer|32nm]] SOI with [[High-k dielectric|HKMG]] arrived in October 2011 for both servers and desktops. The server segment included the dual chip (16-core) [[Opteron]] processor codenamed ''Interlagos'' (for [[Socket G34]]) and single chip (4, 6 or 8 cores) ''Valencia'' (for [[Socket C32]]), while the ''Zambezi'' (4, 6 and 8 cores) targeted desktops on [[Socket AM3+]].<ref>{{citation |url=https://www.amd.com/us/press-releases/Pages/amd-analyst-day-2009nov11.aspx |title=Analyst Day 2009 Summary |date=November 11, 2009 |publisher=[[AMD]] |access-date=2009-11-14}}</ref><ref>{{citation|url=http://www.planet3dnow.de/cgi-bin/newspub/viewnews.cgi?id=1282840508 |title=AMD bestätigt: "Zambezi" ist inkompatibel zum Sockel AM3 |publisher=Planet3dnow.de |access-date=2012-01-23}}</ref>

Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit [[Fused multiply–add|FMA]]-capable [[Floating-point unit|FPUs]] which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer also introduced shared L2 cache in the new architecture. AMD calls this ''design'' a "Module". A 16-core processor design would feature eight of these "modules",<ref>{{citation |url=http://phx.corporate-ir.net/phoenix.zhtml?c=74093&p=irol-analystday |title=Analyst Day 2009 Presentations |date=November 11, 2009 |publisher=[[AMD]] |access-date=2009-11-14}}</ref> but the operating system will recognize each "module" as two logical cores.

The modular architecture consists of multithreaded shared L2 cache and FlexFPU, which uses [[simultaneous multithreading]]. Each physical integer core, two per module, is single threaded, in contrast with Intel's [[Hyperthreading]], where two virtual simultaneous threads share the resources of a single physical core.<ref>{{Cite web |url=http://cdn3.wccftech.com/wp-content/uploads/2013/07/AMD-Steamroller-vs-Bulldozer.jpg |title=Archived copy |access-date=2013-07-22 |archive-date=2013-10-17 |archive-url=https://web.archive.org/web/20131017014731/http://cdn3.wccftech.com/wp-content/uploads/2013/07/AMD-Steamroller-vs-Bulldozer.jpg |url-status=dead }}</ref><ref>{{cite web|url=https://www.bit-tech.net/news/hardware/2010/10/28/amd-unveils-flex-fp/1|title=AMD unveils Flex FP - bit-tech.net|website=bit-tech.net}}</ref>

In a retrospective review, Jeremy Laird of [[APC (magazine)|APC]] magazine commented on Bulldozer issues, noted that it was slower than outgoing Phenom II K10 design, and that the PC software ecosystem had not yet "embraced" the multi-threaded model. By his observation, issues caused a big loss for AMD, that the company lost over 1 billion [[United States dollar|USD]] in 2012, and that some industry observers were predicting the bankruptcy by mid-2015. The company later managed to return to profit. Mentioned reasons for regaining the profitability were the earlier [[Divestment|divesting]] of in-house manufacturing into [[GlobalFoundries]] and then outsourcing the manufacturing to [[TSMC]] and making a new [[Ryzen]] CPU design.<ref name=":0">{{Cite magazine |last=Laird |first=Jeremy |date=August 2022 |title=Ryzen again: The resurrection of AMD |magazine=[[APC (magazine)|APC]] |language=English |publisher=Future Publishing |issue=509 |pages=56–57 |issn=0725-4415}}</ref>

== Architecture ==

=== {{Anchor|CIC|CMT}}Bulldozer core ===
[[File:AMD Bulldozer block diagram (CPU core block).png|thumb|right|300px|Block diagram of a complete Bulldozer module, showing '''2 integer clusters''']]
[[File:AMD Bulldozer block diagram (8 core CPU).PNG|thumb|right|300px|Block diagram of a 4 module design with '''8 integer clusters''']]
[[File:Hwloc.png|thumb|right|300px|Memory topology of a Bulldozer server]]
[[File:Bulldozer 640.jpg|thumb|Bulldozer die shot with highlighted parts]]
Bulldozer made use of "Clustered Multithreading" (CMT), a technique where some parts of the processor are shared between two threads and some parts are unique for each thread. Prior examples of such an approach to unconventional [[multithreading (computer architecture)|multithreading]] can be traced way back to the 2005 [[UltraSPARC T1|Sun Microsystems' UltraSPARC T1]] CPU.
In terms of hardware complexity and functionality, a Bulldozer CMT module is equal to a dual-core processor in its integer calculation capabilities, and to either a single-core processor or a handicapped dual-core in terms of floating-point computational power, depending on whether the code is saturated in floating point instructions in both threads running on the same CMT module, and whether the FPU is performing 128-bit or 256-bit floating point operations. The reason for this is that for each two integer cores, that is, within the same module, there is a single floating-point unit consisting of a pair of 128-bit [[FMAC]] [[execution unit]]s.

CMT is in some way a simpler but similar design philosophy to [[simultaneous multithreading|SMT]]; both designs try to utilize execution units efficiently; in either method, when two threads compete for some execution pipelines, there is a loss in performance in one or more of the threads. Due to dedicated integer cores, the Bulldozer family modules performed roughly like a dual-core, dual-threaded processor during sections of code that were either wholly integer or a mix of integer and floating-point calculations; yet, due to the SMT use of the shared floating-point pipelines, the module would perform similarly to a single-core, dual-threaded SMT processor (SMT2) for a pair of threads saturated with floating-point instructions. (Both of these last two comparisons make the assumption that the processor possesses an equally wide and capable execution core, integer-wise and floating-point-wise, respectively.)

Both CMT and SMT are at peak effectiveness while running integer and floating point code on a pair of threads. CMT stays at peak effectiveness while working on a pair of threads consisting both of integer code, while under SMT, one or both threads will underperform due to competition for integer execution units. The disadvantage for CMT is a greater number of idle integer execution units in a single threaded case. In the single threaded case, CMT is limited to use at most half of the integer execution units in its module, while SMT imposes no such limit. A large SMT core with integer circuitry as wide and fast as two CMT cores could in theory have momentarily up to twice an integer performance in a single thread case. (More realistically for general code as a whole, [[Pollack's Rule]] estimates a speedup factor of <math>\sqrt{2}</math>, or approximately 40% increase in performance.)

CMT processors and a typical SMT processor are similar in their efficient shared use of the L2 cache between a pair of threads.

* A module consists of a coupling of two "conventional" x86 out of order processing cores. The processing core shares the early pipeline stages (e.g. [[CPU cache|L1i]], fetch, decode), the FPUs, and the L2 cache with the rest of the module.
** Each module has the following independent hardware resources:<ref>{{citation | url=http://images.anandtech.com/reviews/cpu/amd/hotchips2010/bulldozeruarch.jpg | title=Bulldozer microarchitecture block | date=August 24, 2010 | publisher=[[AnandTech]]}}</ref><ref>{{citation | url=http://www.xbitlabs.com/images/news/2010-08/bulldozer_3_aug2010.png | title=Bulldozer module functional schematic | date=August 24, 2010 | publisher=[[AMD]] | access-date=August 25, 2010 | archive-date=October 1, 2012 | archive-url=https://web.archive.org/web/20121001061921/http://www.xbitlabs.com/images/news/2010-08/bulldozer_3_aug2010.png | url-status=dead }}</ref>
** 16&nbsp;KB 4-way of L1d (way-predicted) per core and 2-way 64&nbsp;KB of L1i per module, one way for each of the two cores<ref>{{citation|url=http://www.tomshardware.com/reviews/bulldozer-bobcat-hot-chips,2724-2.html |title=More On Bulldozer |publisher=Tomshardware.com |date=2010-08-24 |access-date=2012-01-23}}</ref><ref>{{citation |author=AMD Reveals Details About Bulldozer Microprocessors |url=http://www.xbitlabs.com/news/cpu/display/20100824154814_AMD_Unveils_Details_About_Bulldozer_Microprocessors.html |title=AMD Reveals Details About Bulldozer Microprocessors |publisher=Xbitlabs.com |access-date=2012-01-23 |archive-date=2011-09-03 |archive-url=https://web.archive.org/web/20110903124338/http://www.xbitlabs.com/news/cpu/display/20100824154814_AMD_Unveils_Details_About_Bulldozer_Microprocessors.html |url-status=dead }}</ref><ref>{{citation|author=Real World Technologies |url=http://www.realworldtech.com/page.cfm?ArticleID=RWT082610181333&p=4 |title=AMD's Bulldozer Microarchitecture |publisher=Realworldtech.com |date=2010-08-26 |access-date=2012-01-23}}</ref>
** 2&nbsp;MB of L2 cache per module (shared between the two integer cores)
**Write Coalescing Cache<ref>{{cite web|url=http://www.realworldtech.com/bulldozer/9/|title=AMD's Bulldozer Microarchitecture Memory Subsystem Continued|date=August 26, 2010|author=David Kanter|website=Real World Technologies}}</ref> is a special cache that is part of L2 cache in Bulldozer microarchitecture. Stores from both L1D caches in the module go through the WCC, where they are buffered and coalesced. The WCC's task is reducing number of writes to the L2 cache.
** Two dedicated integer cores
*** – ''each one includes two [[Arithmetic logic unit|ALU]] and two [[Address generation unit|AGU]] which are capable of a total of four independent arithmetic and memory operations per clock and per core''
*** – ''duplicating integer schedulers and execution pipelines offers dedicated hardware to each of two threads which double performance for multi-threaded integer loads''
*** – ''the second integer core in the module increases the Bulldozer module die by around 12%, which at chip level adds about 5% of total die space''<ref>{{citation | url=http://images.anandtech.com/reviews/cpu/amd/hotchips2010/bulldozerefficient.jpg | title=Bulldozer design power efficiency | date=August 24, 2010 | publisher=[[AMD]]}}</ref>
** Two symmetrical 128-bit FMAC ([[fused multiply–add]] capability) floating-point pipelines per module that can be unified into one large 256-bit-wide unit if one of the integer cores dispatches AVX instruction and two symmetrical x87/MMX/SSE capable FPPs for backward compatibility with SSE2 non-optimized software. Each FMAC unit is also capable of division and square root operations with variable latency.
* All modules present share the L3 cache as well as an Advanced Dual-Channel Memory Sub-System (IMC – Integrated Memory Controller).
* A module has 213 million transistors in an area of 30.9&nbsp;mm² (including the 2&nbsp;MB shared L2 cache) on an Orochi die.<ref name="ISSCC 2011"/>
* The pipeline depth of Bulldozer (as well as Piledriver and Steamroller) is 20 cycles, compared to 12 cycles of the K10 core predecessor.<ref>{{citation|url=http://www.anandtech.com/show/5057/the-bulldozer-aftermath-delving-even-deeper/2 |title= The Bulldozer Aftermath: Delving Even Deeper |author= Johan De Gelas }}</ref>
The longer pipeline allowed the Bulldozer family of processors to achieve a much higher clock frequency compared to its K10 predecessors. While this increased frequencies and throughput, the longer pipeline also increased latencies and increased [[branch misprediction]] penalties.
* The width of the Bulldozer integer core, four (2 ALU, 2 AGU), is somewhat less than the width of the K10 core, six (3 ALU, 3 AGU). Bobcat and Jaguar also used a four wide integer core, yet with lighter execution units: 1 ALU, 1 simple ALU, 1 load AGU, 1 store AGU.<ref>{{citation|author= Anand Lal Shimpi | url= http://www.anandtech.com/show/6976/amds-jaguar-architecture-the-cpu-powering-xbox-one-playstation-4-kabini-temash | title=AMD's Jaguar Architecture: The CPU Powering Xbox One, PlayStation 4, Kabini & Temash}}</ref>
The issue widths (and peak instruction executions per cycle) of a Jaguar, K10, and Bulldozer core are 2, 3, and 4 respectively. This made Bulldozer a more superscalar design compared to Jaguar/Bobcat. However, due to K10's somewhat wider core (in addition to the lack of refinements and optimizations in a first generation design) the Bulldozer architecture typically performed with somewhat [[Instructions per cycle|lower IPC]] compared to its K10 predecessors. It was not until the refinements made in Piledriver and Steamroller, that the IPC of the Bulldozer family distinctly began to exceed that of K10 processors such as Phenom II.

===[[Branch predictor]]===
*Two-level Branch Target Buffer(BTB)<ref>{{cite web|title=Bulldozer Overview |url=https://www.olcf.ornl.gov/wp-content/uploads/2012/01/TitanWorkshop2012_Day1_AMD.pdf |first=Ted |last=Barragy |date=January 23, 2012 |access-date=September 19, 2024 }}</ref>
*Hybrid predictor for conditionals
*Indirect predictor

=== Instruction set extensions ===
* Support for Intel's Advanced Vector Extensions ([[Advanced Vector Extensions|AVX]]) instruction set, which supports 256-Bit floating point operations, and [[SSE4.1]], [[SSE4.2]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], as well as future 128-bit instruction sets proposed by AMD ([[XOP instruction set|XOP]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], and [[F16C]]),<ref>{{citation|url=http://techreport.com/discussions.x/16871 |title=XOP and FMA4 Instruction set in SSE5 |publisher=Techreport.com |date=2009-05-06 |access-date=2012-01-23}}</ref> which have the same functionality as the [[SSE5]] instruction set formerly proposed by AMD, but with compatibility to the [[Advanced Vector Extensions|AVX]] coding scheme.
*Bulldozer GEN4 ([[Excavator (microarchitecture)|Excavator]]) supports [[AVX2]] instruction sets.

=== Process technology and clock frequency ===
* 11-metal layer 32&nbsp;nm SOI process with implemented first generation [[GlobalFoundries]]'s [[High-K Metal Gate]] (HKMG)
* ''Turbo Core 2'' performance boost to increase clock frequency up to 500&nbsp;MHz with all threads active (for most workloads) and up to 1&nbsp;GHz with the half of the thread active, within the TDP limit.<ref>{{citation |url=http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-2010analystday |title=AMD Financial Analyst Day 2010, Server Platforms Presentation |publisher=Ir.amd.com |date=2010-11-09 |access-date=2012-01-23 |archive-date=2013-11-12 |archive-url=https://web.archive.org/web/20131112230543/http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-2010analystday |url-status=dead }}</ref>
* The chip operates at 0.775 to 1.425&nbsp;V, achieving clock frequencies of 3.6&nbsp;GHz or more<ref name="ISSCC 2011" />
* Min-Max TDP: 25 – 140&nbsp;watts

=== Cache and memory interface ===
* Up to 8&nbsp;MB of L3 shared among all cores on the same silicon die (8&nbsp;MB for 4 cores in Desktop segment and 16&nbsp;MB for 8 cores in the Server segment), divided into four subcaches of 2&nbsp;MB each, capable of operating at 2.2&nbsp;GHz at 1.1125&nbsp;V<ref name="ISSCC 2011">{{citation |url=http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf |title=AP |access-date=2012-01-23 |archive-date=2012-01-20 |archive-url=https://web.archive.org/web/20120120082428/http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf |url-status=dead }}</ref>
* Native [[Ddr3|DDR3]] memory support up to DDR3-1866<ref name="AMD Roadmap">{{citation|url=http://news.ati-forum.de/images/stories/Szymanski/News/2010/zambezi_roadmap.jpg |title=AMD Roadmap |access-date=2012-01-23}}</ref>
* Dual Channel DDR3 integrated memory controller for Desktop and Server/Workstation Opteron 42xx "Valencia";<ref>{{citation|url=https://www.amd.com/us/Documents/Opteron_4000_QRG.pdf |title=AMD Opteron 4200 Series Processor Quick Reference Guide |author=AMD |publisher=www.amd.com |date=2012-05-14 |access-date=2012-08-15}}</ref> Quad Channel DDR3 Integrated Memory Controller<ref>{{citation|url=https://www.amd.com/us/Documents/Opteron_6000_QRG.pdf |title=AMD Opteron 6200 Series Processor Quick Reference Guide |author=AMD |publisher=www.amd.com |date=2012-05-14 |access-date=2012-08-15}}</ref> for Server/Workstation Opteron 62xx "Interlagos"
* AMD claims support for two DIMMs of DDR3-1600 per channel. Two DIMMs of DDR3-1866 on a single channel will be down-clocked to 1600.

=== I/O and socket interface ===
* [[HyperTransport]] Technology rev. 3.1 (''3.20&nbsp;GHz, 6.4&nbsp;GT/s, 25.6&nbsp;GB/s & 16-bit wide link'') [first implemented into HY-D1 revision [[List of AMD Opteron microprocessors#Opteron 6100-series "Magny-Cours" (45 nm)|"Magny-Cours"]] on the socket G34 Opteron platform in March 2010 and [[List of AMD Opteron microprocessors#Opteron 4100-series "Lisbon" (45 nm) 2|"Lisbon"]] on the socket C32 Opteron platform in June 2010]
* [[Socket AM3+]] (''AM3r2'')
** 942-pin, [[DDR3 SDRAM|DDR3]] support only
** Will retain backward compatibility with Socket AM3 motherboards (as per motherboard manufacturer choice and if BIOS updates are provided<ref>{{citation |url=http://event.asus.com/2011/mb/AM3_PLUS_Ready/ |title=ASUS confirms AM3+ compatibility on AM3 boards |publisher=Event.asus.com |access-date=2012-01-23 |archive-date=2013-06-06 |archive-url=https://web.archive.org/web/20130606121219/http://event.asus.com/2011/mb/AM3_PLUS_Ready/ |url-status=dead }}</ref><ref>{{citation|url=http://www.legitreviews.com/msi-boards-support-amd-am3-multi-core-processors_10404 |title=MSI confirms AM3+ compatibility on AM3 boards |date=April 2011 |publisher=Event.msi.com |access-date=2012-01-23}}</ref>), however this not officially supported by AMD; AM3+ motherboards will be backward-compatible with AM3 processors.<ref>{{Cite web|url=http://www.extremetech.com/article2/0,2845,2368186,00.asp|archiveurl=https://web.archive.org/web/20101210224414/http://www.extremetech.com/article2/0%2C2845%2C2368186%2C00.asp|url-status=dead|title=AM3 processors will work in the AM3+ socket, but Bulldozer chips will not work in non-AM3+ motherboards|archivedate=December 10, 2010}}</ref>
* For the server segment, the existing [[socket G34]] (LGA1974) and [[socket C32]] (LGA1207) will be used.

== Features ==
{{empty section|date=March 2023}} <!-- Template:AMD x86 CPU features was deleted per oldid=1142398499#Template:AMD_x86_CPU_features -->

== Processors ==
{{Main article|List of AMD FX processors|List of AMD processors with 3D graphics|Opteron}}
[[File:AMD Bulldozer chipset.PNG|thumb|right|250px|Chipset and I/Os for 1st CMT generation]]
[[File:AMD FX 8350 Prozessor.jpg|thumb|AMD FX 8350 Processor]]
[[File:AMD Opteron 6282 SE (OS6282YETGGGU)-top.jpg|thumb|AMD Opteron 6282 processor]]

The first revenue shipments of Bulldozer-based Opteron processors was announced on September 7, 2011.<ref>{{citation |title=AMD Ships First "Bulldozer" Processors|url=https://finance.yahoo.com/news/AMD-Ships-First-Bulldozer-iw-1483835751.html?x=0}}</ref> The FX-4100, FX-6100, FX-8120 and FX-8150 were released in October 2011; with remaining FX series AMD processors released at the end of the first quarter of 2012.

=== Desktop ===
{| class="wikitable" style="text-align:center"
|-
! rowspan="2" | Model
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]<br />[[#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan="2" | Freq.<br />(GHz)
! colspan="2" | Max. turbo<br />(GHz)
! rowspan="2" | L2<br />cache
! rowspan="2" | L3<br />(MB)
! rowspan="2" | TDP<br />(W)
! rowspan="2" | DDR3<br />Memory
! rowspan="2" | Turbo<br />Core<br />2.0
! rowspan="2" | Socket
|-
! Full<br />load
! Half<br />load
|-
| FX-8100
| rowspan="5" | [4]8
| 2.8
| 3.1
| 3.7
| rowspan="5" | 4×
2MB
| rowspan="11" | 8
| 95
| rowspan="14" | 1866
| rowspan="14" | Yes
| rowspan="14" | [[Socket AM3+|AM3+]]
|-
| FX-8120
| 3.1
| 3.4
| 4.0
| 125
|-
| FX-8140
| 3.2
| 3.6
| 4.1
| 95
|-
| FX-8150
| 3.6
| 3.9
| 4.2
| rowspan="2" | 125
|-
| FX-8170
| 3.9
| 4.2
| 4.5
|-
| FX-6100
| rowspan="4" | [3]6
| 3.3
| 3.6
| 3.9
| rowspan="4" | 3×
2MB
| rowspan="3" | 95
|-
| FX-6120
| 3.6
| 3.9
| 4.2
|-
| FX-6130
| 3.6
| 3.8
| 3.9
|-
| FX-6200
| 3.8
| 4.0
| 4.1
| 125
|-
| FX-4100
| rowspan="5" | [2]4
| 3.6
| 3.7
| 3.8
| rowspan="5" | 2×
2MB
| rowspan="2" | 95
|-
| FX-4120
| 3.9
| 4.0
| 4.1
|-
| FX-4130
| 3.8
| rowspan="2" | 3.9
| rowspan="2" | 4.0
| 4
| 125
|-
| FX-4150
| 3.8
| rowspan="2" | 8
| 95/125
|-
| FX-4170
| 4.2
| colspan="2" | 4.3
| 125
|}
Major Sources: CPU-World<ref>{{citation|url=http://www.cpu-world.com/CPUs/Bulldozer/TYPE-FX-Series.html |title=AMD FX-Series processor families |publisher=Cpu-world.com |date=2012-10-02 |access-date=2012-10-21}}</ref> and Xbit-Labs<ref>{{cite web |url=http://www.xbitlabs.com/news/cpu/display/20120921231354_AMD_Sets_the_FX_Vishera_Launch_Date.html |title=AMD Sets the FX "Vishera" Launch Date | access-date = 2012-09-23 |last=Shilov |first=Anton |date=2012-09-21 |work=X-bit laboratories |publisher=X-bit labs |url-status=dead |archive-url=https://web.archive.org/web/20120924062818/http://www.xbitlabs.com/news/cpu/display/20120921231354_AMD_Sets_the_FX_Vishera_Launch_Date.html |archive-date=2012-09-24 }}</ref>

=== Server ===
There are two series of [[Opteron#Opteron (32 nm SOI) – First Generation Bulldozer Microarchitecture|Bulldozer-based processors for servers]]: [[Opteron]] 4200 series ([[Socket C32]], code named Valencia, with up to four modules) and Opteron 6200 series ([[Socket G34]], code named Interlagos, with up to 8 modules).<ref>{{citation |title=What Is Bulldozer? |url=http://blogs.amd.com/work/2010/08/02/what-is-bulldozer/ |date=2010-08-02 |url-status=dead |archive-url=https://web.archive.org/web/20100806023754/http://blogs.amd.com/work/2010/08/02/what-is-bulldozer/ |archive-date=August 6, 2010 }}</ref><ref>{{citation |title=AMD Opteron 6200 series microprocessor family |url=http://www.cpu-world.com/CPUs/Bulldozer/TYPE-Opteron%206200%20series.html |publisher=cpu-world.com}}</ref>

== False advertising lawsuit ==
In November 2015, AMD was sued under the [[California Consumers Legal Remedies Act]] and [[California Unfair Competition Law|Unfair Competition Law]] for allegedly misrepresenting the specifications of Bulldozer chips. The class-action lawsuit, filed on 26 October in the US District Court for the Northern District of California, claims that each Bulldozer module is in fact a single CPU core with a few dual-core traits, rather than a true dual-core design.<ref name="ars-fxlawsuit">{{cite news|title=AMD sued over allegedly misleading Bulldozer core count|url=https://arstechnica.com/gadgets/2015/11/amd-sued-over-allegedly-misleading-bulldozer-core-count/|access-date=8 November 2015|work=Ars Technica}}</ref> In August 2019, AMD agreed to settle the suit for $12.1M.<ref name="AT-fxsettlement">{{cite news|title=AMD Bulldozer 'Core' Lawsuit: AMD Settles for $12.1m, Payouts for Some|url=https://www.anandtech.com/show/14804/amd-settlement|access-date=19 January 2021|work=AnandTech}}</ref><ref name="AMDCPUsettlementWS">{{cite web|title=Tony Dickey and Paul Parmer, et al. v. Advanced Micro Devices|url=https://www.amdcpusettlement.com/|access-date=19 January 2021|archive-url=https://web.archive.org/web/20191019090206/https://www.amdcpusettlement.com/|archive-date=19 October 2019}}</ref>

== Performance ==

=== Performance on Linux ===
On 24 October 2011, the first generation tests done by [[Phoronix]] confirmed that the performance of Bulldozer CPU was somewhat less than expected.<ref>{{citation|url=https://www.phoronix.com/scan.php?page=article&item=amd_fx8150_bulldozer&num=1|title=AMD FX-8150 Bulldozer On Ubuntu Linux |publisher=phoronix.com |date=2011-10-24 |access-date=2012-12-13}}</ref> In several tests, the CPU performed similarly to the older generation Phenom 1060T.

The performance later substantially increased, as various compiler optimizations and CPU driver fixes were released.<ref>{{citation|url=https://www.phoronix.com/vr.php?view=16648|title=AMD Bulldozer Cache Aliasing Issue Fix |publisher=phoronix.com}}</ref><ref>{{citation|url=https://www.phoronix.com/vr.php?view=17265|title=AMD's FX-8150 Bulldozer Benefits From New Compilers, Tuning |publisher=phoronix.com}}</ref>

=== Performance on Windows ===
The first Bulldozer CPUs were met with a mixed response. It was discovered that the FX-8150 performed poorly in benchmarks that were not highly threaded, falling behind the second-generation Intel Core i* series processors and being matched or even outperformed by AMD's own Phenom II X6 at lower clock speeds. In highly threaded benchmarks, the FX-8150 performed on par with the Phenom II X6, and the [[Intel Core#Core i7 2|Intel Core i7 2600K]], depending on the benchmark. Given the overall more consistent performance of the [[Intel Core#Core i5 2|Intel Core i5 2500K]] at a lower price, these results left many reviewers underwhelmed. The processor was found to be extremely [[Power management|power-hungry]] under load, especially when overclocked, compared to [[Sandy Bridge (microarchitecture)|Intel's Sandy Bridge]].<ref>{{citation |url=http://www.xbitlabs.com/articles/cpu/display/amd-fx-8150_13.html#sect0 |title=Bulldozer Has Arrived: AMD FX-8150 Processor Review |page=13 |publisher=X-bit labs |date=2011-10-11 |access-date=2012-01-23 |archive-date=2012-01-13 |archive-url=https://web.archive.org/web/20120113020207/http://www.xbitlabs.com/articles/cpu/display/amd-fx-8150_13.html#sect0 |url-status=dead }}</ref><ref>{{citation |url=http://www.xbitlabs.com/articles/cpu/display/amd-fx-8150_14.html#sect0 |title=Bulldozer Has Arrived: AMD FX-8150 Processor Review |page=14 |publisher=X-bit labs |date=2011-10-11 |access-date=2012-01-23 |url-status=dead |archive-url=https://web.archive.org/web/20120116023404/http://www.xbitlabs.com/articles/cpu/display/amd-fx-8150_14.html#sect0 |archive-date=2012-01-16 }}</ref>

On 13 October 2011, AMD stated on its blog that "there are some in our community who feel the product performance did not meet their expectations", but showed benchmarks on actual applications where it outperformed the Sandy Bridge i7 2600k and AMD X6 1100T.<ref>{{citation|url=http://blogs.amd.com/play/2011/10/13/our-take-on-amd-fx/ |title=Our Take on AMD FX |publisher='akozak' on behalf of AMD Blogs |date=2011-10-13 |access-date=23 January 2012 |archive-url=https://web.archive.org/web/20111015090212/http://blogs.amd.com/play/2011/10/13/our-take-on-amd-fx/ |archive-date=15 October 2011 |url-status=dead}}</ref>

In January 2012, Microsoft released two hotfixes for Windows 7 and Server 2008 R2 that marginally improve the performance of Bulldozer CPUs by addressing the thread scheduling concerns raised after the release of Bulldozer.<ref>{{citation|url=http://support.microsoft.com/kb/2645594/en |title=An update is available for computers that have an AMD FX, AMD Opteron 4200, AMD Opteron 6200, or AMD Bulldozer series processor installed and that are running Windows 7 or Windows Server 2008 R2 |publisher=support.microsoft.com |date=January 2012 |access-date=2014-02-11}}</ref><ref>{{citation|url=http://support.microsoft.com/kb/2646060/en |title=An update that selectively disables the Core Parking feature in Windows 7 or in Windows Server 2008 R2 is available |publisher=support.microsoft.com |date=January 2012 |access-date=2014-02-11}}</ref><ref>{{cite web|url=http://www.tomshardware.com/reviews/windows-7-hotfix-bulldozer-performance,3119.html|title=AMD's FX-8150 After Two Windows 7 Hotfixes And UEFI Updates|date=24 January 2012|website=tomshardware.com}}</ref>

On 6 March 2012, AMD posted a knowledge base article stating that there was a compatibility problem with FX processors, and certain games on the widely used digital game distribution platform, [[Steam (service)|Steam]]. AMD stated that they had provided a [[BIOS]] update to several motherboard manufacturers (namely: [[Asus]], [[Gigabyte Technology]], [[Micro-Star International|MSI]], and [[ASRock]]) that would fix the problem.<ref>{{citation|url=http://support.amd.com/en-us/kb-articles/Pages/STEAMGamesonAMDFXplatforms.aspx |title=STEAM Games on AMD FX platforms |publisher=support.amd.com |date=2012-06-12 |access-date=2012-10-11}}</ref>

In September 2014, AMD CEO Rory Read conceded the Bulldozer design had not been a "game-changing part", and that AMD had to live with the design for four years.<ref>{{cite web|url=http://www.pcgamer.com/amd-next-generation-microarchitecture-will-make-up-for-muted-bulldozer-reception/|title=AMD: next-generation microarchitecture will make up for muted Bulldozer reception|website=pcgamer.com}}</ref>

=== Overclocking ===
On 31 August 2011, AMD and a group of well-known overclockers including Brian McLachlan, Sami Mäkinen, Aaron Schradin, and Simon Solotko managed to set a new world record for CPU frequency using the unreleased and overclocked FX-8150 Bulldozer processor. Before that day, the record sat at 8.309&nbsp;GHz, but the Bulldozer combined with [[liquid helium]] [[Computer cooling|cooling]] reached a new high of 8.429&nbsp;GHz. The record has since been overtaken at 8.58&nbsp;GHz by Andre Yang using [[liquid nitrogen]].<ref>{{citation |url=http://www.geek.com/articles/chips/amd-bulldozer-cpu-beats-world-record-again-achieving-8-461ghz-2011111/ |title=AMD Bulldozer CPU beats world record again achieving 8.461GHz |publisher=geek.com |date=2011-11-01 |access-date=2012-10-16 |archive-date=2012-04-28 |archive-url=https://web.archive.org/web/20120428193028/http://www.geek.com/articles/chips/amd-bulldozer-cpu-beats-world-record-again-achieving-8-461ghz-2011111 |url-status=dead }}</ref><ref>{{cite web|url=http://www.tomshardware.com/news/fx-8150-bulldozer-record-overclocking-speed,13903.html|title=AMD Bulldozer Speed Record Broken Again at 8.58GHz|date=5 November 2011|website=tomshardware.com}}</ref> On August 22, 2014 and using an FX-8370 (Piledriver), The Stilt from Team Finland achieved a maximum CPU frequency of 8.722&nbsp;GHz.<ref>{{cite web|url=http://valid.canardpc.com/vytt61|title=CPU-Z Validator 4.0|author=Samuel D.|access-date=23 September 2014}}</ref>

The CPU clock frequency records set by overclocked Bulldozer CPUs were only broken almost a decade later by overclocks of Intel's 13th generation Core [[Raptor Lake]] CPUs in October 2022.<ref>{{Cite web |title=Intel Core i9 13900K @ 8812.85 MHz - CPU-Z VALIDATOR |url=https://valid.x86.fr/k3dwcu |access-date=2022-10-23 |website=valid.x86.fr |language=en}}</ref>

== Revisions ==
''[[Piledriver (microarchitecture)|Piledriver]]'' is the AMD codename for its improved second-generation microarchitecture based on ''Bulldozer''. AMD ''Piledriver'' cores are found in [[Socket FM2]] ''Trinity'' and ''Richland'' based series of APUs and CPUs and the Socket AM3+ ''Vishera'' based FX-series of CPUs. Piledriver was the last generation in the Bulldozer family to be available for socket AM3+ and to be available with an L3 cache. The Piledriver processors available for FM2 (and its mobile variant) sockets did not come with a L3 cache, as the L2 cache is the last-level cache for all FM2/FM2+ processors.

''[[Steamroller (microarchitecture)|Steamroller]]'' is the AMD codename for its third-generation microarchitecture based on an improved version of ''Piledriver''. ''Steamroller'' cores are found in the [[Socket FM2+]] ''Kaveri'' based series of APUs and CPUs.

''[[Excavator (microarchitecture)|Excavator]]'' is the codename for the fourth-generation ''Bulldozer'' core.<ref>{{citation|url=http://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested |title=The Bulldozer Review: AMD FX-8150 Tested |publisher=AnandTech |date=2011-10-12 |access-date=2012-01-23}}</ref> ''Excavator'' was implemented as 'Carrizo' A-series APUs, "Bristol Ridge" A-series APUs, and Athlon x4 CPUs.<ref name="anandtech carizzo">{{Cite web |url=http://www.anandtech.com/show/10009/amd-launches-excavator-on-desktop-the-65w-athlon-x4-845-for-70 |title=AMD launches excavator on desktop: the 65w athlon x4 845 for $70 |last=Cutress |first=Ian |date=2016-02-02 |access-date=2017-03-28 |website=anandtech}}</ref>

== See also ==
* [[List of AMD CPU microarchitectures]]
* [[List of AMD FX microprocessors]]
* [[Charles R. Moore (computer engineer)]]
* [[Alpha 21264]]
* [[AMD K10|K10 (microarchitecture)]]
* [[Bobcat (microarchitecture)]]
* [[Opteron]]
* [[Piledriver (microarchitecture)]]
* [[Steamroller (microarchitecture)]]
* [[Excavator (microarchitecture)]]
* [[Zen (microarchitecture)]]

== References ==
{{Reflist|30em}}

== External links ==
* [https://www.amd.com/en-us/products/processors/desktop/fx www.amd.com/en-us/products/processors/desktop/fx]

{{AMD processors}}
{{AMD processor roadmap}}

{{DEFAULTSORT:Bulldozer (Processor)}}
[[Category:AMD x86 microprocessors]]
[[Category:AMD microarchitectures]]
[[Category:X86 microarchitectures]]