View source for AND-OR-invert

{{Short description|Logic gate type}}
{{More footnotes|date=April 2009}}
'''AND-OR-invert''' (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed from the combination of one or more [[AND gate]]s followed by a [[NOR gate]] (equivalent to an [[OR gate]] through an [[Inverter gate]], which is the "OI" part of "AOI"). Construction of AOI cells is particularly efficient using [[CMOS]] technology, where the total number of transistor gates can be compared to the same construction using [[NAND logic]] or [[NOR logic]]. The complement of AOI logic is [[OR-AND-invert]] (OAI) logic, where the OR gates precede a NAND gate.<ref>[https://dyclassroom.com/boolean-algebra/product-of-sums-reduction-using-karnaugh-map Product of Sums reduction using Karnaugh Map].</ref>

==Overview==
Most [[logic optimization]] result in a [[Canonical normal form|sum-of-products]] or product-of-sums logic expression.<ref>[https://www.electricaltechnology.org/2018/05/sum-of-product-sop-product-of-sum-pos.html Sum Of Product (SOP) & Product Of Sum (POS)].</ref>

AOI is used for sum-of-products, the variables are ANDed to form minterms which are ORed together then inverted:<ref>[https://tams.informatik.uni-hamburg.de/applets/hades/webdemos/10-gates/00-gates/complex.html AOI and OAI complex gates]</ref>
* {{overline|AB + C}}{{space|3}}is known as a AOI 2-1 gate.
* {{overline|AB + CD}}{{space|3}}is known as a AOI 2-2 gate. 
* {{overline|ABC + DEF}}{{space|3}}is known as a AOI 3-3 gate. 
* {{overline|ABCD + EFGH}}{{space|3}}is known as a AOI 4-4 gate. 
* {{overline|ABCDE + FGH + JK}}{{space|3}}is known as a AOI 4-3-2 gate.
* and other variations.

==Examples==
AOI gates perform one or more [[logical and|AND]] operations followed by an [[logical or|OR]] operation then an inversion.

===2-1 AOI gate===
[[File:AOI21Symbol.svg|thumb|right|Symbol for 2-1 AOI gate. The AND gate has inputs A and B (per table).]]

The 2-1 AOI gate can be represented by the following [[Boolean algebra (logic)|boolean equation]] and [[truth table]]:

: <math>Q = \overline{(A \wedge B) \vee C}.</math>

{| class="wikitable" 
|- bgcolor="#ddeeff" align="center"
|colspan=3|'''INPUT'''<br>A &nbsp; B &nbsp; C || '''OUTPUT'''<br> Q
|- 
|{{no2|0}} || {{no2|0}} || {{no2|0}} || {{yes2|1}}
|- 
|{{no2|0}} || {{no2|0}} || {{yes2|1}} || {{no2|0}}
|- 
|{{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|- 
|{{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|- 
|{{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}}
|- 
|{{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}}
|- 
|{{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{no2|0}}
|- 
|{{yes2|1}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}

===2-2 AOI gate===
[[File:AOI22Symbol.svg|thumb|right|Symbol for 2-2 AOI gate]]
Real world examples of an 2-2 AOI gate are found in the CD4085B, SN74LS51, SN5450 logic ICs (see further below).<ref name="TI-CD4085B-DS"/><ref name="TI-SN74LS51-DS"/><ref name="TI-SN5450-DS"/>

The 2-2 AOI gate can be represented by the following [[Boolean algebra (logic)|boolean equation]] and [[truth table]]:

: <math>Q = \overline{(A \wedge B) \vee (C \wedge D)}.</math>

{| class="wikitable" 
|- bgcolor="#ddeeff" align="center"
|colspan=4|'''INPUT'''<br>A &nbsp; B &nbsp; C &nbsp; D || '''OUTPUT'''<br> Q
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}}
|-
| {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{yes2|1}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}} || {{no2|0}}
|-
| {{yes2|1}} || {{yes2|1}} || {{yes2|1}} || {{yes2|1}} || {{no2|0}}
|}

===3-3 AOI gate===
Real world examples of an 3-3 AOI gate is found in the SN74LS51 logic IC (see further below).<ref name="TI-SN74LS51-DS"/>

The 3-3 AOI gate can be represented by the following [[Boolean algebra (logic)|boolean equation]] and [[truth table]]:

: <math>Q = \overline{(A \wedge B \wedge C) \vee (D \wedge E \wedge F)}.</math>

Its logic table would have 64 entries, but is not shown.

===4-4 AOI gate===
[[File:Aoi gate.png|thumb|right|Symbol for 4-4 AOI gate]]
Real world examples of an 4-4 AOI gate is found in the CD4048B logic IC (see further below).<ref name="TI-CD4048B-DS"/>

The 4-4 AOI gate can be represented by the following [[Boolean algebra (logic)|boolean equation]] and [[truth table]]:

: <math>Q = \overline{(A \wedge B \wedge C \wedge D) \vee (E \wedge F \wedge G \wedge H)}.</math>

Its logic table would have 256 entries, but is not shown.

==Extensions to multiple levels==
It is possible to create multi-level compound gates, which combine the logic of AND-OR-Invert gates with [[OR-AND-invert]] gates.<ref>{{Cite web |url=https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_03_Logik_Gatter.pptx.pdf |title=Aussagenlogik und Gatter |access-date=2024-01-21 |last=Fischer |first=P. |publisher=University of Heidelberg}}</ref> An example is shown below. The parts implementing the same logic have been put in boxes with the same color.
[[File:AOAI gate with colorboxes.svg|thumb|
compound logic gate for {{overline|(CD&nbsp;+&nbsp;B)&nbsp;A}}, plus CMOS version.]]

==Electronic implementation==
[[File:AOI21 complex vs standard gates.svg|thumb|right|An AOI21 logic gate in CMOS using a complex gate (left) and standard gates (right)]]
AND-OR-invert (AOI) and OAI gates can be readily implemented in [[CMOS]] circuitry. AOI gates are particularly advantaged in that the total number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately. This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a 2-1 AOI gate can be constructed with 6 transistors in CMOS, compared to 10 transistors using a 2-input NAND gate (4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors).

In [[NMOS logic]], the lower half of the CMOS circuit is used in combination with a load device or pull-up transistor (typically a [[Depletion-load NMOS logic|depletion load]] or a [[Dynamic logic (digital electronics)|dynamic load]]).

AOI gates are similarly efficient in [[transistor–transistor logic]] (TTL).

;Examples

CMOS [[4000-series integrated circuits|4000-series]] logic family:
* CD4085B = dual 2-2 AOI gate<ref name="TI-CD4085B-DS">{{cite web |title=CD4085B Datasheet |url=https://www.ti.com/lit/gpn/cd4085b |date=2003 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20190305101600/http://www.ti.com/lit/ds/symlink/cd4085b.pdf |archive-date=March 5, 2019 |url-status=live}}</ref>
* CD4086B = single expandable 2-2-2-2 AOI gate"<ref>{{cite web |title=CD4086B Datasheet |url=https://www.ti.com/lit/gpn/cd4086b |date=2003 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20190415005543/http://www.ti.com/lit/ds/symlink/cd4086b.pdf |archive-date=April 15, 2019 |url-status=live}}</ref>
* CD4048B = single expandable 8-input 8-function with [[Three-state logic|three-state]] output, 8 choices for gate type: 8 NOR / 8 OR / 8 NAND / 8 AND / 4-4 AND-OR-Invert / 4-4 AND-OR / 4-4 OR-AND-Invert / 4-4 OR-AND<ref name="TI-CD4048B-DS">{{cite web |title=CD4048B Datasheet |url=https://www.ti.com/lit/gpn/cd4048b |date=2003 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20190305101456/http://www.ti.com/lit/ds/symlink/cd4048b.pdf |archive-date=March 5, 2019 |url-status=live}}</ref>

TTL [[7400-series integrated circuits|7400-series]] logic family: (in past decades, a number of AOI parts were available in the 7400 family, but currently most are obsolete (no longer manufactured))
* SN5450 = dual 2-2 AOI gate, one is expandable<ref name="TI-SN5450-DS">{{cite web |title=SN5450 Datasheet |url=https://www.ti.com/lit/gpn/sn5450 |date=1988 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20180726135055/http://www.ti.com/lit/ds/symlink/sn5450.pdf |archive-date=July 26, 2018 |url-status=live}}</ref> (SN54 is military version of SN74)
* SN74LS51 = 2-2 AOI gate and 3-3 AOI gate<ref name="TI-SN74LS51-DS">{{cite web |title=SN74LS51 Datasheet |url=https://www.ti.com/lit/gpn/sn74ls51 |date=1988 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20201130214103/https://www.ti.com/lit/ds/symlink/sn74ls51.pdf |archive-date=November 30, 2020 |url-status=live}}</ref>
* SN54LS54 = single 2-3-3-2 AOI gate<ref>{{cite web |title=SN54LS54 Datasheet |url=https://www.ti.com/lit/gpn/sn54ls54 |date=1988 |website=[[Texas Instruments]] |archive-url=https://web.archive.org/web/20180305202426/http://www.ti.com/lit/ds/symlink/sn54ls54.pdf |archive-date=March 5, 2018 |url-status=live}}</ref>

<gallery class="center" widths="200px" heights="200px">
File:Logique74ls51.svg|Schematic of SN74LS51 IC consists of a 3-3 AOI gate and 2-2 AOI gate<ref name="TI-SN74LS51-DS"/>
File:Ttl inside 7451.svg|Pinout of SN74LS51 IC<ref name="TI-SN74LS51-DS"/>
</gallery>

==See also==
{{Commons category}}
* [[List of 7400-series integrated circuits]]
* [[List of 4000-series integrated circuits]]

==References==
{{Reflist}}
*{{cite book |title=Engineering digital design: Revised Second Edition |last = Tinder |first=Richard F. |year=2000 |isbn=0-12-691295-5 |pages=317–319 |publisher = Academic Press |url=https://books.google.com/books?id=6x0pjjMKRh0C&dq=AOI+gate&pg=PT347 |accessdate=2008-07-04}}
*{{cite book |title=Application-Specific Integrated Circuits |last=John |first= Michael |year=1997 |url=http://iroi.seu.edu.cn/books/asics/Book2/CH02/CH02.4.htm#pgfId=799 |accessdate= 2008-07-04}}

[[Category:Logic gates|AOI gate]]