View source for 7 nm process

{{short description|MOSFET technology node}}
{{Technical|date=January 2020}}
{{Semiconductor manufacturing processes}}
{{third-party|date=September 2024}}
In [[semiconductor manufacturing]], the '''"7 nm" process''' is a term for the [[MOSFET]] [[technology node]] following the [[10 nm process|"10 nm"]] node, defined by the [[International Roadmap for Devices and Systems]] (IRDS), which was preceded by the [[International Technology Roadmap for Semiconductors]] (ITRS). It is based on [[FinFET]] (fin field-effect transistor) technology, a type of [[multi-gate MOSFET]] technology.

As of 2021, the IRDS Lithography standard gives a table of dimensions for the "7 nm" node,<ref>{{Cite web |date=7 April 2024 |title=International Roadmap for Devices and Systems 2021 Update: Lithography |url=https://irds.ieee.org/images/files/pdf/2021/2021IRDS_Litho.pdf |website=International Roadmap for Devices and Systems}}</ref> with examples given below:
{| class="wikitable"
|+
!Calculated Value
!nm
|-
|Minimum half pitch (DRAM, MPU metal)
|18
|-
|Minimum half pitch (Flash, MPU fin, LGAA)
|15
|-
|Minimum required overlay (OL) (DRAM, Flash, MPU)
|3.6
|-
|Gate pitch
|54
|-
|Gate length
|20
|}
The 2021 IRDS Lithography standard is a retrospective document, as the first volume production of a "7 nm" branded process was in 2016 with Taiwan Semiconductor Manufacturing Company's ([[TSMC]]) production of 256Mbit [[static random-access memory|SRAM]] memory chips using a "7[[nanometre|nm]]" process called N7.<ref name="tsmc" /> [[Samsung]] started mass production of their "7nm" process (7LPP) devices in 2018.<ref name="autogenerated1">{{cite web |last1=Chen |first1=Monica |last2=Shen |first2=Jessie |date=22 June 2018 |title=TSMC ramping up 7nm chip production |url=https://www.digitimes.com/news/a20180622PD204.html |access-date=September 17, 2022 |work=DigiTimes}}</ref> These process nodes had the same approximate [[transistor density]] as Intel's "''10 nm Enhanced Superfin''" node, later rebranded "Intel 7."<ref>{{Cite web |last=Subramaniam |first=Vaidyanathan |date=27 July 2021 |title=Intel details new process innovations and node names, Alder Lake 10 nm Enhanced SuperFin is now Intel 7; Intel 20A is the 2 nm process for 2024 |url=https://www.notebookcheck.net/Intel-details-new-process-innovations-and-node-names-Alder-Lake-10-nm-Enhanced-SuperFin-is-now-Intel-7-Intel-20A-is-the-2-nm-process-for-2024.552398.0.html |website=Notebook Check}}</ref> 

Since at least 1997, the length scale of a process node has not referred to any particular dimension on the integrated circuits, such as gate length, metal pitch, or gate pitch, as new lithography processes no longer uniformly shrank all features on a chip. By the late 2010s, the length scale had become a commercial name<ref name="urlNo More Nanometers – EEJournal">{{cite web |last1=Morris |first1=Kevin |date=July 23, 2020 |title=No More Nanometers: It's Time for New Node Naming |url=https://www.eejournal.com/article/no-more-nanometers/ |website=Electronic Engineering Journal |access-date=September 17, 2022}}</ref> that indicated a new generation of process technologies, without any relation to physical properties.<ref>{{cite web |last1=Shukla |first1=Priyank |title=A Brief History of Process Node Evolution |url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html |website=Design-Reuse |access-date=July 9, 2019}}</ref><ref>{{cite web |last1=Hruska |first1=Joel |date=June 23, 2014 |title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists… |url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists |website=ExtremeTech |access-date=September 17, 2022}}</ref><ref>{{cite web |last1=Pirzada |first1=Usman |date=September 16, 2016 |title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022 |url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/ |website=Wccftech |access-date=September 17, 2022}}</ref>  Previous ITRS and IRDS standards had insufficient guidance on process node naming conventions to address the widely varying dimensions on a chip, leading to a divergence between how foundries branded their lithography and the actual dimensions their process nodes achieved. 

The first mainstream "7nm" mobile processor intended for mass market use, the [[Apple Inc.|Apple]] [[Apple A12|A12 Bionic]], was announced at Apple's September 2018 event.<ref>{{Cite news |last1=Shankland |first1=Stephen |date=September 12, 2018 |title=Apple's A12 Bionic CPU for the new iPhone XS is ahead of the industry moving to 7nm chip manufacturing tech |url=https://www.cnet.com/news/iphone-xs-a12-bionic-chip-is-industry-first-7nm-cpu/ |work=CNET |access-date=September 16, 2018}}</ref> Although [[Huawei]] announced its own "7nm" processor before the Apple A12 Bionic, the [[HiSilicon#Kirin 980|Kirin 980]] on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips were manufactured by TSMC.<ref>{{Cite news |last1=Summers |first1=N. |date=September 12, 2018 |title=Apple's A12 Bionic is the first 7-nanometer smartphone chip |url=https://www.engadget.com/2018/09/12/apple-a12-bionic-7-nanometer-chip/ |work=Engadget |language=en-US |access-date=September 20, 2018}}</ref>

In 2019,<ref>{{cite web |date=August 8, 2019 |title=AMD Launches Epyc Rome, First 7nm CPU |url=https://www.hpcwire.com/2019/08/08/amd-launches-epyc-rome-first-7nm-cpu/ |archive-url=https://web.archive.org/web/20190815203730/https://www.hpcwire.com/2019/08/08/amd-launches-epyc-rome-first-7nm-cpu/ |archive-date=2019-08-15}}</ref> AMD released their "[[Epyc#Second generation Epyc (Rome)|Rome]]" (EPYC 2) processors for servers and datacenters, which are based on TSMC's N7{{nbsp}}node<ref name="anandtech">{{cite news |last1=Smith |first1=Ryan |title=AMD "Rome" EPYC CPUs to Be Fabbed By TSMC |url=https://www.anandtech.com/show/13122/amd-rome-epyc-cpus-to-be-fabbed-by-tsmc |access-date=18 June 2019 |work=[[AnandTech]] |date=July 26, 2018}}</ref> and feature up to 64 cores and 128 threads.  They also released their "[[Zen 2|Matisse]]" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome [[multi-chip module]] (MCM) is fabricated with the [[GlobalFoundries|GlobalFoundries']] 14nm (14HP) process, while the Matisse's I/O die uses the [[GlobalFoundries]]' "12nm" (12LP+) process. The [[Radeon RX 5000 series|Radeon RX 5000]] series is also based on TSMC's N7 process.

==History==
{{prose|section|date=November 2021}}

=== Technology Demonstrations ===

In the early 2000s, researchers began demonstrating 7nm level [[MOSFET]]s , with an [[IBM]] team including Bruce Doris, Omer Dokumaci, Meikei Ieong, and Anda Mocuta successfully fabricating a 6nm [[silicon-on-insulator]] (SOI) MOSFET.<ref>{{cite web|url=http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor|archive-url=https://web.archive.org/web/20110531040504/http://www.theinquirer.net/inquirer/news/1034321/ibm-claims-worlds-smallest-silicon-transistor|archive-date=May 31, 2011|title=IBM claims world's smallest silicon transistor - TheINQUIRER|website=Theinquirer.net|access-date=7 December 2017|date=2002-12-09}}</ref><ref>{{cite book |last1=Doris |first1=Bruce B. |last2=Dokumaci |first2=Omer H. |last3=Ieong |first3=Meikei K. |last4=Mocuta |first4=Anda |last5=Zhang |first5=Ying |last6=Kanarsky |first6=Thomas S. |last7=Roy |first7=R. A. |title=Digest. International Electron Devices Meeting |chapter=Extreme scaling with ultra-thin Si channel MOSFETs |date=December 2002 |pages=267–270 |doi=10.1109/IEDM.2002.1175829|isbn=0-7803-7462-2 |s2cid=10151651 }}</ref> Shortly after, in 2003, [[NEC]]'s researchers Hitoshi Wakabayashi and Shigeharu Yamagami advanced further by fabricating a 5nm MOSFET.<ref>{{cite web |title=NEC test-produces world's smallest transistor |url=http://www.thefreelibrary.com/NEC+test-produces+world's+smallest+transistor.-a0111295563 |website=The Free Library |access-date=December 7, 2017}}</ref><ref>{{cite book |last1=Wakabayashi |first1=Hitoshi |last2=Yamagami |first2=Shigeharu |last3=Ikezawa |first3=Nobuyuki |last4=Ogura |first4=Atsushi |last5=Narihiro |first5=Mitsuru |last6=Arai |first6=K. |last7=Ochiai |first7=Y. |last8=Takeuchi |first8=K. |last9=Yamamoto |first9=T. |last10=Mogami |first10=T. |title=IEEE International Electron Devices Meeting 2003 |chapter=Sub-10-nm planar-bulk-CMOS devices using lateral junction control |date=December 2003 |pages=20.7.1–20.7.3 |doi=10.1109/IEDM.2003.1269446 |isbn=0-7803-7872-5 |s2cid=2100267}}</ref> 

In July 2015, IBM announced that they had built the first functional transistors with "7nm" technology, using a [[silicon-germanium]] process.<ref>{{Cite web|url=https://www.zdnet.com/article/ibm-research-builds-functional-7nm-processor/|title=IBM Research builds functional 7nm processor|first=Larry|last=Dignan|website=ZDNet}}</ref><ref>{{Cite news|url=https://www.nytimes.com/2015/07/09/technology/ibm-announces-computer-chips-more-powerful-than-any-in-existence.html|title=IBM Discloses Working Version of a Much Higher-Capacity Chip|first=John|last=Markoff|newspaper=The New York Times|date=July 9, 2015}}</ref><ref>{{Cite web|url=https://arstechnica.com/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/?amp=1|title=Beyond silicon: IBM unveils world's first 7nm chip – Ars Technica|website=arstechnica.com|date=July 9, 2015 }}</ref><ref>{{Cite web |title=Seven Advancements for Beyond 7nm Chips |url=https://www.ibm.com/blogs/research/2017/02/ibm-spie-seven-advancements-beyond-7nm-chips/ |website=IBM Research Blog |date=February 27, 2017}}</ref> With further development in February 2017, [[TSMC]] produced 256Mbit SRAM memory cells at with their "7nm" process, with a cell area of 0.027 square [[Micrometre|micrometers]],<ref>{{Cite book |last1=Chang |first1=J. |last2=Chen |first2=Y. |last3=Chan |first3=W. |last4=Singh |first4=S. P. |last5=Cheng |first5=H. |last6=Fujiwara |first6=H. |last7=Lin |first7=J. |last8=Lin |first8=K. |last9=Hung |first9=J. |last10=Lee |first10=R. |last11=Liao |first11=H. |title=2017 IEEE International Solid-State Circuits Conference (ISSCC) |chapter=12.1 a 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-V<sub>MIN</sub> applications |date=February 2017 |chapter-url=https://ieeexplore.ieee.org/document/7870333 |pages=206–207|doi=10.1109/ISSCC.2017.7870333|isbn=978-1-5090-3758-2 |s2cid=19930825}}</ref> giving a square minimum feature size: 
<math> F^2 = \cfrac{0.027nn^2}{(0.07nn)^2} = 550 </math>

This cumulated in TSMC starting volume of 7nm production in 2018.<ref name="tsmc">{{cite web |title=7nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/7nm.htm |publisher=TSMC |access-date=June 30, 2019}}</ref>

===Expected commercialization and technologies===
{{proseline|date=February 2024}}
In 2015, Intel expected that at the 7nm node, III-V semiconductors would have to be used in transistors, signaling a shift away from silicon.<ref>{{cite web | url=https://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/ | title=Intel forges ahead to 10nm, will move away from silicon at 7nm | date=February 23, 2015 }}</ref>

In April 2016, TSMC announced that "7nm" trial production would begin in the first half of 2017.<ref>{{cite web |last=Parish |first=Kevin |date=April 20, 2016 |title=Watch out Intel and Samsung: TSMC is gearing up for 7&nbsp;nm processing with trial production |url=https://www.digitaltrends.com/computing/tsmc-7nm-2017/ |website=Digital Trends |access-date=September 17, 2022}}</ref> In April 2017, TSMC began risk production of 256Mbit SRAM memory chips using a "7nm" (N7FF+) process,<ref name="tsmc"/> with [[extreme ultraviolet lithography]] (EUV).<ref>{{Cite web|url=http://www.eetimes.com/document.asp?doc_id=1331489&page_number=2|title=TSMC Tips 7+, 12, 22nm Nodes {{!}} EE Times|website=EETimes|access-date=2017-03-17}}</ref> TSMC's "7nm" production plans, as of early 2017,{{and then what|date=February 2024}} was to use deep ultraviolet (DUV) immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation "7nm" (N7FF+) production was planned{{and then what|date=February 2024}} to use EUV multiple patterning and have an estimated transition from risk to volume manufacturing between 2018 and 2019.<ref>{{cite web |last=Shilov |first=Anton |date=5 May 2017 |title=Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC |url=http://www.anandtech.com/show/11337/samsung-and-tsmc-roadmaps-12-nm-8-nm-and-6-nm-added/2 |website=AnandTech |access-date=September 17, 2022}}</ref>

In September 2016, [[GlobalFoundries]] announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.<ref>{{cite press release |title=GLOBALFOUNDRIES to Deliver Industry's Leading-Performance Offering of 7&nbsp;nm FinFET Technology |url=http://www.globalfoundries.com/news-events/press-releases/globalfoundries-deliver-industrys-leading-performance-offering-7nm-finfet |website=GlobalFoundries |date=September 15, 2016 |access-date=April 8, 2017}}</ref>

In February 2017, [[Intel]] announced Fab 42 in [[Chandler, Arizona]], which was according to press releases at that time expected{{and then what|date=February 2024}} to produce microprocessors using a "7nm" (Intel 4<ref name=":3" />) manufacturing process.<ref>{{Cite web |title=Intel Supports American Innovation with $7 Billion Investment in Next-Generation Semiconductor Factory in Arizona |url=https://newsroom.intel.com/news-releases/intel-supports-american-innovation-7-billion-investment-next-generation-semiconductor-factory-arizona/ |website=Intel Newsroom |date=February 8, 2017 |access-date=September 17, 2022}}</ref> The company had not, at that time, published any expected values for feature lengths at this process node.{{and then what|date=February 2024}}

In April 2018, TSMC announced volume production of "7nm" (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.<ref name=autogenerated1 />

In May 2018, [[Samsung]] announced production of "7nm" (7LPP) chips for later that year. ASML Holding NV is their main supplier of EUV lithography machines.<ref>{{cite web |last1=King |first1=Ian |date=May 22, 2018 |title=Samsung Says New 7-Nanometer Chip Production Starting This Year |url=https://www.bloomberg.com/news/articles/2018-05-22/samsung-says-new-7-nanometer-chip-production-starting-this-year |website=Bloomberg |access-date=September 17, 2022}}</ref>

In August 2018, GlobalFoundries announced it was stopping development of "7nm" chips, citing cost.<ref>{{cite web |last1=Dent |first1=Steve |date=August 28, 2018 |title=Major AMD chip supplier will no longer make next-gen chips |url=https://www.engadget.com/2018/08/28/global-foundries-stops-7-nanometer-chip-production/ |website=Engadget |access-date=September 17, 2022}}</ref>

On October 28, 2018, Samsung announced their second generation "7nm" process (7LPP) had entered risk production and was at that time expected to have entered mass production by 2019.{{and then what|date=February 2024}}

On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers would have "different flavors" of second generation "7nm".<ref name="q42018">Q4 2018 TSMC earnings call transcript, January 17, 2019.</ref>{{and then what|date=February 2024}}

On April 16, 2019, TSMC announced their "6nm" process called (CLN6FF, N6), which was, according to a press release made on April 16, 2019, at that time expected to have been in mass products from 2021.<ref name=":0">{{Cite web |last1=Schor |first1=David |date=April 16, 2019 |title=TSMC Announces 6-Nanometer Process |url=https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/ |website=WikiChip Fuse |language=en-US |access-date=May 31, 2019}}</ref>{{and then what|date=February 2024}} N6 was at that time expected to have used EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.<ref>{{Cite web |last=Shilov |first=Anton |date=May 1, 2019 |title=TSMC: Most 7nm Clients Will Transition to 6nm |url=https://www.anandtech.com/show/14290/tsmc-most-7nm-clients-will-transit-to-6nm |website=AnandTech |access-date=May 31, 2019}}</ref>

On July 28, 2019, TSMC announced their second gen "7nm" process called N7P, which was projected to have been DUV-based like their N7 process.<ref name=n7p>{{Cite web |last=Schor |first=David |date=July 28, 2019 |title=TSMC Talks 7nm, 5nm, Yield, And Next-Gen 5G And HPC Packaging|url=https://fuse.wikichip.org/news/2567/tsmc-talks-7nm-5nm-yield-and-next-gen-5g-and-hpc-packaging/ |website=WikiChip Fuse |language=en-US |access-date=September 13, 2019}}</ref> Since N7P was fully IP-compatible with the original "7nm", while N7+ (which uses EUV) was not, N7+ (announced earlier as "7nm+") was to have been a separate process from "7nm". N6 ("6nm"), another EUV-based process, was at that time planned to have been released later than even TSMC's "5nm" (N5) process, with the IP-compatibility with N7. At their Q1 2019 earnings call, TSMC reiterated their Q4 2018 statement<ref name=q42018/> that N7+ was at that time expected to have generated less than $1 billion TWD in revenue in 2019.<ref>C. C. Wei, TSMC Q1 2019 earnings call (April 18) transcript.</ref>{{and then what|date=February 2024}}

On October 5, 2019, AMD announced their [[Epyc|EPYC]] Roadmap, featuring Milan chips built using TSMC's N7+ process.<ref>{{Cite web |last1=Alcorn |first1=Paul |date=October 5, 2019 |title=AMD Dishes on Zen 3 and Zen 4 Architecture, Milan and Genoa Roadmap |url=https://www.tomshardware.com/news/amd-zen-3-zen-4-epyc-rome-milan-genoa-architecture-microarchitecture,40561.html |website=Tom's Hardware |language=en-US |access-date=October 8, 2019}}</ref>{{and then what|date=February 2024}}

On October 7, 2019, TSMC announced they had started delivering N7+ products to market in high volume.<ref>{{Cite web|url=https://www.planet3dnow.de/cms/51707-tsmcs-n7-technology-is-first-euv-process-delivering-customer-products-to-market-in-high-volume/|title=TSMC's N7+ Technology is First EUV Process Delivering Customer Products to Market in High Volume {{!}} Planet 3DNow!|date=October 7, 2019 |language=de-DE|access-date=2019-10-08}}</ref>{{and then what|date=February 2024}}

On July 26, 2021, Intel announced their new manufacturing roadmap, renaming all of their future process nodes.<ref name=":3">{{Cite web|last=Cutress|first=Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}}</ref> Intel's "10nm" Enhanced SuperFin (10ESF), which was roughly equivalent to TSMC's N7 process, would thenceforth be known as "Intel 7", while their earlier "7nm" process would erstwhile be called "Intel 4".<ref name=":3" /><ref>{{cite web |title=Accelerating Process Innovation |url=https://download.intel.com/newsroom/2021/client-computing/accelerating-process-innovation.pdf |website=Intel |date=July 26, 2021}}</ref> As a result, Intel's first processors based on Intel 7 were at that time planned to have started shipping by the second half of 2022,{{and then what|date=February 2024}} whereas Intel announced earlier that they were planning to have launched "7nm" processors in 2023.<ref>{{Cite web |last1=Jones |first1=Ryan |date=March 27, 2021 |title=Ctrl+Alt+Delete: Why you should be excited for Intel's 7nm processor |url=https://www.trustedreviews.com/news/why-you-should-be-excited-for-intels-7nm-processor-4129639 |website=Trusted Reviews |language=en |access-date=March 30, 2021}}</ref>{{and then what|date=February 2024}}

===Technology commercialization===
In June 2018, [[Advanced Micro Devices|AMD]] announced 7nm [[Radeon Instinct]] GPUs launching in the second half of 2018.<ref>{{cite press release|url=https://www.amd.com/en-us/press-releases/Pages/pushing-boundaries-for-2018jun05.aspx|date=June 5, 2018|title=Pushing Boundaries for CPUs and GPUs, AMD Shows Next-Generation of Ryzen, Radeon and EPYC Product Leadership at Computex 2018}}</ref> In August 2018, the company confirmed the release of the GPUs.<ref>{{Cite web |last1=Martin |first1=Dylan |date=August 23, 2018 |title=AMD CTO: 'We Went All In' On 7nm CPUs |url=https://www.crn.com/news/components-peripherals/amd-cto-we-went-all-in-on-7nm-cpus |website=CRN |access-date=September 17, 2022}}</ref>

On August 21, 2018, [[Huawei]] announced their [[HiSilicon#Kirin 980|HiSilicon Kirin 980]] SoC to be used in their [[Huawei Mate 20|Huawei Mate 20 and Mate 20 Pro]] built using TSMC's 7nm (N7) process.{{and then what|date=February 2024}}

On September 12, 2018, [[Apple Inc.|Apple]] announced their [[Apple A12|A12 Bionic]] chip used in [[iPhone XS]] and [[iPhone XR]] built using TSMC's 7nm (N7) process. The A12 processor became the first 7nm chip for mass market use as it released before the Huawei Mate 20.<ref>{{cite web|title=Apple Announces 'iPhone Xs' and 'iPhone Xs Max' With Gold Color, Faster Face ID, and More|date=September 12, 2018 |url=https://www.macrumors.com/2018/09/12/apple-announces-iphone-xs/|language=en}}</ref><ref>{{Cite news |last1=Freedman |first1=Andrew E. |date=September 12, 2018 |title=Apple Introduces 7nm A12 Bionic CPU for iPhone XS |url=https://www.tomshardware.com/news/apple-a12-bionic-iphone-xs,37786.html |work=Tom's Hardware |language=en-US |access-date=September 12, 2018}}</ref> On October 30, 2018, Apple announced their [[Apple A12X|A12X Bionic]] chip used in [[iPad Pro]] built using TSMC's 7nm (N7) process.<ref>{{Cite news |last1=Axon |first1=Samuel |date=November 7, 2018 |title=Apple walks Ars through the iPad Pro's A12X system on a chip |url=https://arstechnica.com/gadgets/2018/11/apple-walks-ars-through-the-ipad-pros-a12x-system-on-a-chip/ |work=Ars Technica |language=en-US |access-date=November 18, 2018}}</ref>

On December 4, 2018, [[Qualcomm]] announced their [[Qualcomm Snapdragon|Snapdragon]] [[List of Qualcomm Snapdragon systems-on-chip#Snapdragon 855 and 8cx (2019)|855 and 8cx]] built using TSMC's 7nm (N7) process.<ref>{{Cite web |last1=Cutress |first1=Ian |date=December 4, 2018 |title=Qualcomm Tech Summit, Day 1: Announcing 5G Partnerships and Snapdragon 855 |url=https://www.anandtech.com/show/13662/qualcomm-tech-summit-day-1-announcing-5g-partnerships-and-snapdragon-855 |website=AnandTech |access-date=May 31, 2019}}</ref> The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.<ref>{{Cite web |last1=Frumusanu |first1=Andrei |date=December 18, 2018 |title=Lenovo First to a Snapdragon 855 Phone with Announcement of Z5 Pro GT |url=https://www.anandtech.com/show/13728/lenovo-first-to-a-snapdragon-855-phone-with-announcement-of-z5-pro-gt |website=AnandTech |access-date=May 31, 2019}}</ref>

On May 29, 2019, [[MediaTek]] announced their [[5G]] [[System on a chip|SoC]] built using a TSMC 7nm process.<ref>{{Cite web |title=MediaTek 5G |url=https://i.mediatek.com/mediatek-5g |website=MediaTek |language=en |access-date=May 31, 2019}}</ref>

On July 7, 2019, AMD officially launched their [[Ryzen]] 3000 series of central processing units, based on the TSMC 7nm process and [[Zen 2]] microarchitecture.

On August 6, 2019, [[Samsung Electronics|Samsung]] announced their Exynos 9825 SoC, the first chip built using their 7LPP process. The Exynos 9825 is the first mass market chip built featuring [[Extreme ultraviolet lithography|EUVL]].<ref>{{Cite web |last1=Siddiqui |first1=Aamir |date=August 7, 2019 |title=Samsung announces Exynos 9825 prior to Galaxy Note 10 launch |url=https://www.xda-developers.com/samsung-exynos-9825-announced-galaxy-note-10-launch/ |website=XDA-Developers |language=en-US |access-date=September 13, 2019}}</ref>

On September 6, 2019, Huawei announced their [[HiSilicon#Kirin 990 4G & 990 5G|HiSilicon Kirin 990 4G & 990 5G]] SoCs, built using TSMC's N7 and N7+ processes.<ref>{{Cite web |last1=Cutress |first1=Ian |title=Huawei Announces Kirin 990 and Kirin 990 5G: Dual SoC Approach, Integrated 5G Modem |url=https://www.anandtech.com/show/14851/huawei-announces-kirin-990-and-kirin-990-5g-dual-soc-approach-integrated-5g-modem |website=AnandTech |access-date=September 13, 2019}}</ref>

On September 10, 2019, Apple announced their [[Apple A13|A13 Bionic]] chip used in [[iPhone 11]] and [[iPhone 11 Pro]] built using TSMC's 2nd gen N7P process.<ref name=":2">{{Cite web |title=IBM Reveals Next-Generation IBM POWER10 Processor |url=https://newsroom.ibm.com/2020-08-17-IBM-Reveals-Next-Generation-IBM-POWER10-Processor |website=IBM Newsroom |date=August 17, 2020 |access-date=August 17, 2020}}</ref><!-- Apple did not confirm it was TSMC's N7P or N7+ process. However, TSMC started shipping N7+ in high volume in October, confirming the A13 is N7P. https://www.planet3dnow.de/cms/51707-tsmcs-n7-technology-is-first-euv-process-delivering-customer-products-to-market-in-high-volume/ -->

7nm (N7 nodes) manufacturing made up 36% of TSMC's revenue in the second quarter of 2020.<ref>{{Cite web|url=https://www.extremetech.com/computing/314204-tsmc-plots-an-aggressive-course-for-3nm-lithography-and-beyond|title = TSMC Plots an Aggressive Course for 3nm Lithography and Beyond - ExtremeTech}}</ref>

On August 17, 2020, IBM announced their [[Power10]] processor.<ref name=":2"/>

On July 26, 2021, Intel announced that their [[Alder Lake (microprocessor)|Alder Lake]] processors would be manufactured using their newly rebranded "Intel 7" process, previously known as "10nm Enhanced SuperFin".<ref name=":3"/> These processors were, at that time, expected based on press releases to have been planned to have been released in the second half of 2021.{{and then what|date=February 2024}} The company earlier confirmed a 7nm, now called "Intel 4",<ref name=":3"/> microprocessor family called Meteor Lake to be released in 2023.<ref>{{Cite web |title=Intel CEO Announces 'IDM 2.0' Strategy for Manufacturing, Innovation |url=https://newsroom.intel.com/news-releases/idm-manufacturing-innovation-product-leadership/ |website=Intel Newsroom |date=March 23, 2021 |access-date=September 17, 2022}}</ref><ref>{{Cite web |title=Intel Unleashed: Engineering the Future (Replay) |url=https://newsroom.intel.com/news/intel-unleashed-engineering-future-video/ |website=Intel Newsroom |date=March 23, 2021 |access-date=September 17, 2022}}</ref>{{and then what|date=February 2024}}

==Patterning difficulties==
[[File:LELE_challenge.png|thumb|left|upright=1.4|'''Pitch splitting issues.''' Successive litho-etch patterning is subject to overlay errors as well as the CD errors from different exposures.]]
[[File:SADP_challenge.png|thumb|left|upright=1.4|'''Spacer patterning issues.''' Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.]]
[[File:Line cut location offset.png|thumb|left|upright=1.4|'''Overlay error impact on line cut.''' An overlay error on a cut hole exposure could distort the line ends (top) or infringe on an adjacent line (bottom).]]
[[File:Two-bar_challenge.png|thumb|right|upright=1.4|'''Two-bar EUV patterning issues.''' In EUV lithography, a pair of features may not have both features in focus at the same time; one will have different size from the other, and both will shift differently through focus as well.]]
[[File:20 nm width stochastic failure probability.png|thumb|right|upright=1.4|'''7nm EUV stochastic failure probability.''' "7nm" features were expected to approach ~20nm width. The probability of EUV stochastic failure is measurably high for the commonly applied dose of 30 mJ/cm<sup>2</sup>.]]

The "7nm" foundry node is expected to utilize any of or a combination of the following patterning technologies: [[Multiple patterning|pitch splitting]], [[Multiple patterning|self-aligned patterning]], and [[EUVL|EUV lithography]]. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.

===Pitch splitting===
Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.

===Spacer patterning===
Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'.<ref>M. J. Maslow et al., Proc. SPIE 10587, 1058704 (2018).</ref> Generally, pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For [[FEOL]] features like gate or active area isolation (e.g. fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.

When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.

Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.

Self-aligned litho-etch-litho-etch (SALELE) has been implemented for "7nm" BEOL patterning.<ref>[https://www.linkedin.com/pulse/salele-double-patterning-7nm-5nm-nodes-frederick-chen SALELE Double Patterning for 7nm and 5nm Nodes]</ref>

===EUV lithography===
[[Extreme ultraviolet lithography]] (also known as '''''EUV''''' or '''''EUVL''''') is capable of resolving features below 20nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus.<ref>{{Cite web|url=https://www.euvlitho.com/2018/P62.pdf|title=IMEC EUVL 2018 Workshop}}</ref><ref>Y. Nakajima et al., EUVL Symposium 2007, Sapporo.</ref><ref>L. de Winter et al., Proc. SPIE 9661, 96610A (2015).</ref> This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.<ref>M. Burkhardt and A. Raghunathan, Proc. SPIE 9422, 94220X (2015).</ref>

EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.<ref>P. De Bisschop and E. Hendrickx, Proc. SPIE 10583, 105831K (2018).</ref><ref>{{Cite web|url=https://www.linkedin.com/pulse/euvs-stochastic-valley-death-frederick-chen|title=EUV's Stochastic Valley of Death|website=linkedin.com}}</ref> The defect level is on the order of 1K/mm<sup>2</sup>.<ref>S. Larivière et al., Proc. SPIE 10583, 105830U (2018).</ref>

The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint.<ref>E. van Setten et al., Proc. SPIE 9661. 96610G (2015).</ref> A separate exposure(s) for cutting lines is preferred.

[[Phase-shift mask|Attenuated phase shift masks]] have been used in production for [[90 nm process|90 nm]] node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193nm),<ref>C-H. Chang et al., Proc. SPIE 5377, 902 (2004).</ref><ref>T. Devoivre et al., MTDT 2002.</ref> whereas this resolution enhancement is not available for EUV.<ref>S-S. Yu et al., Proc. SPIE 8679, 86791L (2013).</ref><ref>A. Erdmann et al., Proc. SPIE 10583, 1058312 (2018).</ref>

At 2021 [[SPIE]]'s EUV Lithography conference, it was reported by a [[TSMC]] customer that EUV contact yield was comparable to immersion multipatterning yield.<ref>Qi Li et al., Proc. SPIE 11609, 116090V (2021).</ref>

===Comparison with previous nodes===
Due to these challenges, "7nm" poses unprecedented patterning difficulty in the [[back end of line]] (BEOL). The previous high-volume, long-lived foundry node (Samsung "10nm", TSMC "16nm") used pitch splitting for the tighter pitch metal layers.<ref>{{Cite book|chapter=10nm 2nd generation BEOL technology with optimized illumination and LELELELE|first1=W. C.|title=2017 Symposium on VLSI Technology|last1=Jeong|first2=J. H.|last2=Ahn|first3=Y. S.|last3=Bang|first4=Y. S.|last4=Yoon|first5=J. Y.|last5=Choi|first6=Y. C.|last6=Kim|first7=S. W.|last7=Paek|first8=S. W.|last8=Ahn|first9=B. S.|last9=Kim|first10=T. J.|last10=Song|first11=J. H.|last11=Jung|first12=J. H.|last12=Do|first13=S. M.|last13=Lim|first14=H.-|last14=Cho|first15=J. H.|last15=Lee|first16=D. W.|last16=Kim|first17=S. B.|last17=Kang|first18=J.-|last18=Ku|first19=S. D.|last19=Kwon|first20=S.-|last20=Jung|first21=J. S.|last21=Yoon|date=June 23, 2017|pages=T144–T145|via=IEEE Xplore|doi=10.23919/VLSIT.2017.7998156|isbn=978-4-86348-605-8|s2cid=43207918}}</ref><ref>{{Cite web|url=https://community.cadence.com/cadence_blogs_8/b/ii/posts/tsmc-symposium-10nm-is-ready-for-design-starts-at-this-moment|title=TSMC Symposium: "10nm is Ready for Design Starts at This Moment" - Industry Insights - Cadence Blogs - Cadence Community|website=community.cadence.com}}</ref><ref>{{Cite book|chapter=A 16nm FinFET CMOS technology for mobile SoC and computing applications|first1=S.|title=2013 IEEE International Electron Devices Meeting|last1=Wu|first2=C. Y.|last2=Lin|first3=M. C.|last3=Chiang|first4=J. J.|last4=Liaw|first5=J. Y.|last5=Cheng|first6=S. H.|last6=Yang|first7=M.|last7=Liang|first8=T.|last8=Miyashita|first9=C. H.|last9=Tsai|first10=B. C.|last10=Hsu|first11=H. Y.|last11=Chen|first12=T.|last12=Yamamoto|first13=S. Y.|last13=Chang|first14=V. S.|last14=Chang|first15=C. H.|last15=Chang|first16=J. H.|last16=Chen|first17=H. F.|last17=Chen|first18=K. C.|last18=Ting|first19=Y. K.|last19=Wu|first20=K. H.|last20=Pan|first21=R. F.|last21=Tsui|first22=C. H.|last22=Yao|first23=P. R.|last23=Chang|first24=H. M.|last24=Lien|first25=T. L.|last25=Lee|first26=H. M.|last26=Lee|first27=W.|last27=Chang|first28=T.|last28=Chang|first29=R.|last29=Chen|first30=M.|last30=Yeh|first31=C. C.|last31=Chen|first32=Y. H.|last32=Chiu|first33=Y. H.|last33=Chen|first34=H. C.|last34=Huang|first35=Y. C.|last35=Lu|first36=C. W.|last36=Chang|first37=M. H.|last37=Tsai|first38=C. C.|last38=Liu|first39=K. S.|last39=Chen|first40=C. C.|last40=Kuo|first41=H. T.|last41=Lin|first42=S. M.|last42=Jang|first43=Y.|last43=Ku|date=December 23, 2013|pages=9.1.1–9.1.4|via=IEEE Xplore|doi=10.1109/IEDM.2013.6724591|isbn=978-1-4799-2306-9}}</ref>

===Cycle time: immersion vs. EUV===
{| class="wikitable"
! style="text-align:left;" | Process
!Immersion (≥ 275 WPH)<ref>{{Cite web|url=https://www.asml.com/en/products|title=Products & services - Supplying the semiconductor industry|website=asml.com}}</ref>
!EUV (1500 wafers/day)<ref name=s7nm>{{Cite web|url=https://www.eetimes.com/samsung-ramps-7nm-euv-chips/|title=Samsung Ramps 7nm EUV Chips|date=October 17, 2018|website=EETimes}}</ref>
|-
! style="text-align:left;" | '''Single'''-patterned layer:<br />1 day completion by immersion
|6000 wafers/day
|1500 wafers/day
|-
! style="text-align:left;" | '''Double'''-patterned layer:<br />2 days completion by immersion
|6000 wafers/2 days
|3000 wafers/2 days
|-
! style="text-align:left;" | '''Triple'''-patterned layer:<br />3 days completion by immersion
|6000 wafers/3 days
|4500 wafers/3 days
|-
! style="text-align:left;" | '''Quad'''-patterned layer:<br />4 days completion by immersion
|6000 wafers/4 days
|6000 wafers/4 days
|-
|}

Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.

==Design rule management in volume production==
The "7nm" metal patterning currently practiced by TSMC involves self-aligned double patterning (SADP) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height.<ref>{{Cite web|url=https://en.wikichip.org/wiki/7_nm_lithography_process|title = 7 nm lithography process - WikiChip}}</ref> However, self-aligned quad patterning (SAQP) is used to form the fin, the most important factor to performance.<ref name="7nmdrc">{{Cite web|title=A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology|url=https://www.design-reuse.com/articles/45832/design-rule-check-drc-violations-asic-designs-7nm-finfet.html|website=Design And Reuse}}</ref> Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.<ref name="7nmdrc" />

==Process nodes and process offerings==
{{Disputed section|Intel 7|date=September 2023}}
The naming of process nodes by 4 different manufacturers (TSMC, Samsung, [[Semiconductor Manufacturing International Corporation|SMIC]], Intel) is partially marketing-driven and not directly related to any measurable distance on a chip{{snd}} for example TSMC's "7nm" node was previously similar in some key dimensions to Intel's planned first-iteration "10nm" node, before Intel released further iterations, culminating in "10nm Enhanced SuperFin", which was later renamed to "Intel 7" for marketing reasons.<ref>{{cite web |last=Merrit |first=Rick |date=16 Jan 2017 |title=15 Views from a Silicon Summit |url=http://www.eetimes.com/document.asp?doc_id=1331185 |work=EETimes |access-date=September 16, 2022}}</ref><ref>{{Cite web |last=Hill |first=Brandon |date=March 28, 2017 |title=Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals |url=https://hothardware.com/news/intel-details-advanced-10nm-node |website=HotHardware |access-date=August 30, 2018 |archive-date=June 12, 2018 |archive-url=https://web.archive.org/web/20180612163405/https://hothardware.com/news/intel-details-advanced-10nm-node}}</ref>

Since EUV implementation at "7nm" is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's "7nm", even with EUV single-patterned 36nm pitch layers, 44nm pitch layers would still be quadruple patterned.<ref name=7nml>J. Kim et al., Proc. SPIE 10962, 1096204 (2019).</ref>

{| class="wikitable" style="text-align:center"
|+ 7nm process nodes and process offerings
! 
! colspan=2|[[Samsung Electronics|Samsung]]
! colspan=4|[[TSMC]]
! [[Intel]]
! colspan=3|[[Semiconductor Manufacturing International Corporation|SMIC]]
|-
! Process name
| 7LPP<ref>{{Cite web |title=VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM |url=https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/ |website=WikiChip |date=August 4, 2018 |access-date=September 16, 2022}}</ref><ref>{{Cite web |title=Samsung Electronics Starts Production of EUV-based 7nm LPP Process |url=https://news.samsung.com/global/samsung-electronics-starts-production-of-euv-based-7nm-lpp-process |website=Samsung Newsroom |date=October 18, 2018 |access-date=September 16, 2022}}</ref>
| 6LPP<ref>{{cite web | url=https://www.anandtech.com/show/15538/samsung-starts-mass-production-at-v1-a-dedicated-euv-fab-for-7nm-6nm-5nm-4nm-3nm-nodes | title=Samsung Starts Mass Production at V1: A Dedicated EUV Fab for 7nm, 6nm, 5nm, 4nm, 3nm Nodes }}</ref>
| N7<ref>IEDM 2016</ref>
| N7P<small></small><ref name="n7p" />
| N7+<ref>{{Cite web|url=https://www.eetimes.com/tsmc-goes-photon-to-cloud/|title=TSMC Goes Photon to Cloud|date=October 4, 2018|website=EETimes}}</ref>
| N6
| Intel 7<ref name=":3" />{{disputed inline|Intel 7|date=September 2023}} (10nm)<ref>{{cite news |last1=Bonshor |first1=Gavin |title=Intel Core i9-13900K and i5-13600K Review: Raptor Lake Brings More Bite |url=https://www.anandtech.com/print/17601/intel-core-i9-13900k-and-i5-13600k-review |access-date=28 September 2023 |work=[[AnandTech]] |date=20 October 2022}}</ref>
| N+1 (>7nm)
| N+2 (7nm)
| 7nm EUV
|-
! style="text-align:left;" | Transistor density (MTr/mm<sup>2</sup>)
| 95.08–100.59<ref>{{cite web | url=https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/ | title=Can TSMC Maintain Their Process Technology Lead | date=July 18, 2023 }}</ref><ref>{{cite web | url=https://fuse.wikichip.org/news/6932/samsung-3nm-gaafet-enters-risk-production-discusses-next-gen-improvements/ | title=Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements | date=July 5, 2022 }}</ref>
| {{unknown}}
| colspan=2|91.2–96.5<ref name="Jones">{{cite web |last1=Jones |first1=Scotten |title=TSMC and Samsung 5nm Comparison |url=https://semiwiki.com/semiconductor-manufacturers/samsung-foundry/8157-tsmc-and-samsung-5nm-comparison/ |website=Semiwiki |date=May 3, 2019 |access-date=30 July 2019}}</ref><ref>{{cite web | url=https://fuse.wikichip.org/news/7048/n3e-replaces-n3-comes-in-many-flavors/ | title=N3E Replaces N3; Comes in Many Flavors | date=September 4, 2022 }}</ref>
| 113.9<ref name="Jones" />
| 114.2<ref name=":0" />
| 100.76–106.1<ref>{{citation| url =https://semiwiki.com/semiconductor-manufacturers/intel/285192-can-tsmc-maintain-their-process-technology-lead/| title = Can TSMC Maintain Their Process Technology Lead | first = Scotten|last = Jones | date = July 18, 2023 }}</ref><ref>{{cite web | url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros | title=Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! }}</ref> 60.41<ref>{{cite web
 |first=David
 |last=Schor
 |url=https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/
 |title=A Look At Intel 4 Process Technology
 |website=WikiChip Fuse
 |date=2022-06-19
}}</ref>
| 89<ref>{{citation| url =https://news.yahoo.com/smic-mass-produces-14nm-nodes-003531507.html| title = SMIC Mass Produces 14nm Nodes, Advances To 5nm, 7nm | date = September 16, 2022 }}</ref>
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | SRAM bit-cell size
| 0.0262 μm<sup>2</sup><ref name=":1" />
| {{unknown}}
| colspan=2|0.027 μm<sup>2</sup><ref name=":1">{{Cite web|url=https://fuse.wikichip.org/news/1479/vlsi-2018-samsungs-2nd-gen-7nm-euv-goes-hvm/|title=VLSI 2018: Samsung's 2nd Gen 7nm, EUV Goes HVM|date=2018-08-04|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}</ref>
| {{unknown}}
| {{unknown}}
| 0.0312 μm<sup>2</sup>
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Transistor gate pitch
| 54nm
| {{unknown}}
| colspan=4|57nm
| 54nm
| 66nm
| 63nm
| {{unknown}}
|-
! style="text-align:left;" | Transistor fin pitch
| 27nm
| {{unknown}}
| colspan=2| N/A
| {{unknown}}
| {{unknown}}
| 34nm
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Transistor fin height
| {{unknown}}
| {{unknown}}
| colspan=2| N/A
| {{unknown}}
| {{unknown}}
| 53nm
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Minimum (metal) pitch
| 46nm
| {{unknown}}
| colspan=4|40nm
| 40nm<ref>{{cite web |last1=Smith |first1=Ryan |date=June 13, 2022 |title=Intel 4 Process Node In Detail: 2x Density Scaling, 20% Improved Performance |url=https://www.anandtech.com/show/17448/intel-4-process-node-in-detail-2x-density-scaling-20-improved-performance |website=AnandTech |access-date=September 17, 2022}}</ref>
| 44nm
| 42nm
| {{unknown}}
|-
! style="text-align:left;" | EUV implementation
| 36nm pitch metal;<ref name="7nml" /><br />20% of total layer set
| {{unknown}}
| colspan=2|None, used self-aligned quad patterning ([[Multiple patterning|SAQP]]) instead
| 4 layers
| 5 layers
| None. Relied on [[Multiple patterning|SAQP]] heavily 
| None
| None 
| Yes (after N+2)
|-
! style="text-align:left;" | EUV-limited wafer output
| 1500 wafers/day<ref name="s7nm" />
| {{unknown}}
| colspan=2|N/A
| ~ 1000 wafers/day<ref>{{Cite web|url=http://www.tsmc.com/uploadfile/ir/quarterly/2018/1yZjH/E/TSMC%201Q18%20transcript.pdf|title=TSMC Q1 2018 earnings call transcript, p.12|access-date=October 14, 2018|archive-date=October 14, 2018|archive-url=https://web.archive.org/web/20181014091359/http://www.tsmc.com/uploadfile/ir/quarterly/2018/1yZjH/E/TSMC%201Q18%20transcript.pdf}}</ref>
| {{unknown}}
| N/A
| {{unknown}}
| {{unknown}}
| {{unknown}}
|-
! style="text-align:left;" | Multipatterning <br />(≥ 2 masks on a layer)
| Fins<br />Gate<br />Vias (double-patterned)<ref name="vlsi">W. C. Jeong et al., VLSI Technology 2017.</ref><br />Metal 1 (triple-patterned)<ref name="vlsi" /><br />44nm pitch metal (quad-patterned)<ref name="7nml" />
| {{unknown}}
| colspan=2|Fins<br />Gate<br />Contacts/vias (quad-patterned)<ref>{{Cite web |last1=Dillinger |first1=Tom |date=March 23, 2017 |title=Top 10 Updates from the TSMC Technology Symposium, Part II |url=https://semiwiki.com/semiconductor-manufacturers/tsmc/6676-top-10-updates-from-the-tsmc-technology-symposium-part-ii/ |website=SemiWiki |access-date=September 16, 2022}}</ref><br />Lowest 10 metal layers
| Same as N7, with reduction on 4 EUV layers
| Same as N7, with reduction on 5 EUV layers
|
| multipatterning with DUV
| multipatterning with DUV
| {{unknown}}
|-
! style="text-align:left;" | Release status
| {{success|2018 risk production}}<br />2019 production
| {{success|2020 production}}
| {{success|2017 risk production}}<br />2018 production<ref name="tsmc"/>
| {{success|2019 production}}
| {{success|2018 risk production<ref name="tsmc"/><br />2019 production}}
| {{success|2020 risk production}}<br />2020 production
| {{success|2021 production}}<ref name=":3">{{Cite web|last=Cutress|first=Ian|title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!|url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros|access-date=2021-07-27|website=www.anandtech.com}}</ref>
| {{success|April 2021 risk production, mass production unknown}}
| {{success|Late 2021 risk production, quietly produced since July 2021}}<ref>{{Cite web |author=Paul Alcorn |date=21 July 2022 |title=China's SMIC Shipping 7nm Chips, Reportedly Copied TSMC's Tech|url=https://www.tomshardware.com/news/china-chipmaker-smics-7nm-process-is-reportedly-copied-from-tsmc-tech|website=Tom's Hardware}}</ref>
| {{no|Cancelled due to US embargo}}
|-
|}

GlobalFoundries' "7nm" 7LP (Leading Performance) process would have offered 40% higher performance or 60%+ lower power with a 2x scaling in density and at a 30-45+% lower cost per die over its "14nm" process. The Contacted Poly Pitch (CPP) would have been 56nm and the Minimum Metal Pitch (MMP) would have been 40nm, produced with Self-Aligned Double Patterning (SADP). A 6T SRAM cell would have been 0.269 square microns in size. GlobalFoundries planned to eventually use EUV lithography in an improved process called 7LP+.<ref>{{Cite web |last1=Jones |first1=Scotten |date=July 8, 2017 |title=Exclusive - GLOBALFOUNDRIES discloses 7nm process detail |url=https://semiwiki.com/semiconductor-manufacturers/globalfoundries/6879-exclusive-globalfoundries-discloses-7nm-process-detail/ |website=SemiWiki |access-date=September 16, 2022}}</ref> GlobalFoundries later stopped all "7nm" and beyond process development.<ref>{{Cite web |last1=Shilov |first1=Anton |last2=Cutress |first2=Ian |date=August 27, 2018 |title=GlobalFoundries Stops All 7nm Development: Opts To Focus on Specialized Processes |url=https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development |website=AnandTech |access-date=July 27, 2021}}</ref>

Intel's new "Intel 7" process, previously known as "10nm Enhanced SuperFin" (10ESF), is based on its previous "10nm" node. The node will feature a 10-15% increase in [[performance per watt]]. Meanwhile, their old "7nm" process, now called "Intel 4", was at that time expected to have been released in 2023.<ref>{{Cite web|title=Intel: Sorry, But Our 7nm Chips Will Be Delayed to 2022, 2023|url=https://www.pcmag.com/news/intel-sorry-but-our-7nm-chips-will-be-delayed-to-2022-2023|access-date=2021-07-27|website=PCMAG|language=en}}</ref>{{and then what|date=February 2024}} Few details about the "Intel 4" node had at that time been made public, although its transistor density had at that time been estimated to be at least 202 million transistors per square millimeter.<ref name=":3" /><ref>{{Cite web|url=https://en.wikichip.org/wiki/7_nm_lithography_process#Intel|title = 7 nm lithography process - WikiChip}}</ref>{{and then what|date=February 2024}} As of 2020, Intel had been experiencing problems with its "Intel 4" process to the point of outsourcing production of its Ponte Vecchio GPUs.<ref>{{Cite web|url=https://www.allaboutcircuits.com/news/intels-7nm-process-six-months-behind-schedule/|title=Intel's 7nm Process Six Months Behind Schedule - News}}</ref><ref>{{Cite web|url=https://arstechnica.com/gadgets/2020/07/as-7nm-schedule-continues-slipping-intel-contemplates-3rd-party-fabs/|title = As 7nm schedule continues slipping, Intel contemplates 3rd-party fabs|date = July 24, 2020}}</ref>{{and then what|date=February 2024}}

==References==
{{Reflist}}

==External links==
* [https://en.wikichip.org/wiki/7_nm_lithography_process 7 nm lithography process]

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[[Category:International Technology Roadmap for Semiconductors lithography nodes|*00007]]
[[Category:Taiwanese inventions]]