View source for 10 nm process

{{For|the length in general and comparison|10 nanometres}}
{{use dmy dates|date=March 2022}}
{{short description|MOSFET technology node}}
{{Semiconductor manufacturing processes}}
In [[semiconductor fabrication]], the [[International Technology Roadmap for Semiconductors]] (ITRS) defines the "'''10 nanometer process'''" as the [[MOSFET]] [[technology node]] following the [[14 nm process|"14 nm"]] node.

Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;<ref name="urlNo More Nanometers – EEJournal">{{cite web |url=https://www.eejournal.com/article/no-more-nanometers/ |title=No More Nanometers – EEJournal |date=23 July 2020 |format= }}</ref> neither gate length, metal pitch or gate pitch on a "10nm" device is ten nanometers.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09}}</ref><ref>{{cite web|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists...|last=Hruska|first=Joel|website=[[ExtremeTech]]}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10}}</ref> For example, [[GlobalFoundries]]' "[[7&nbsp;nm]]" processes are dimensionally similar to Intel's "10&nbsp;nm" process.<ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12}}</ref> TSMC and Samsung's "10&nbsp;nm" processes are somewhere between Intel's "14&nbsp;nm" and "10&nbsp;nm" processes in [[transistor density]]. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.{{Citation needed|date=June 2024}}

All production "10&nbsp;nm" processes are based on [[FinFET]] (fin field-effect transistor) technology, a type of [[multi-gate MOSFET]] technology that is a non-planar evolution of planar [[silicon]] [[CMOS]] technology. [[Samsung]] first started their production of "10&nbsp;nm-class" chips in 2013 for their [[multi-level cell]] (MLC) [[flash memory]] chips, followed by their SoCs using their 10&nbsp;nm process in 2016. [[TSMC]] began commercial production of "10&nbsp;nm" chips in 2016, and [[Intel]] later began production of "10{{nbsp}}nm" chips in 2018.{{and then what|date=February 2024}}

==Background==
The ITRS's original naming of this technology node was "11&nbsp;nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a [[Dynamic random-access memory|DRAM]] was projected to be 11&nbsp;[[Nanometre|nm]].

In 2008, [[Pat Gelsinger]], at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the "10&nbsp;nm" node.<ref>{{cite web|title=Intel's Gelsinger Sees Clear Path To 10nm Chips |author=Damon Poeter |url=http://www.crn.com/hardware/208801780 |archive-url=https://web.archive.org/web/20090425061704/http://www.crn.com/hardware/208801780 |archive-date=2009-04-25 |url-status=live |access-date=2009-06-20 |date=July 2008 }}</ref><ref>{{cite web|title=MIT: Optical lithography good to 12 nanometers |url=http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 |archive-url=https://web.archive.org/web/20120925204010/http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 |archive-date=2012-09-25 |url-status=live |access-date=2009-06-20 }}</ref>

In 2011, Samsung announced plans to introduce the "10{{nbsp}}nm" process the following year.<ref>{{cite news |title=World's Largest Fabrication Facility, Line-16 |url=https://news.samsung.com/global/world%E2%80%99s-largest-memory-fabrication-facility-line-16memory |access-date=21 June 2019 |publisher=[[Samsung]] |date=September 26, 2011}}</ref>{{and then what|date=February 2024}} In 2012, Samsung announced [[eMMC]] [[flash memory]] chips that are produced using the "10{{nbsp}}nm" process.<ref>{{cite news |title=Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better |url=https://www.engadget.com/2012/11/15/samsung-10nm-64gb-emmc-mobile-flash-memory/ |access-date=21 June 2019 |work=[[Engadget]] |date=November 15, 2012}}</ref>

As of 2018, "10&nbsp;nm" as it was generally understood was only in high-volume production at [[Samsung]]. [[GlobalFoundries]] had skipped "10&nbsp;nm",{{and then what|date=February 2024}} [[Intel]] had not yet started high-volume "10&nbsp;nm" production, due to yield issues,{{and then what|date=February 2024}} and [[TSMC]] had considered "10&nbsp;nm" to be a short-lived node,<ref>{{Cite web |url=http://techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ |title=10nm rollout |access-date=2018-08-04 |archive-date=2018-08-04 |archive-url=https://web.archive.org/web/20180804110423/http://techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ |url-status=dead }}</ref> mainly dedicated to processors for [[Apple Inc.|Apple]] during 2017–2018, moving on to "[[7 nm]]" in 2018.{{and then what|date=February 2024}}

There is also a distinction to be made between "10&nbsp;nm" as marketed by foundries and "10&nbsp;nm" as marketed by DRAM companies.

==Technology production history==
In April 2013, Samsung announced that it had begun [[mass production]] of [[multi-level cell]] (MLC) [[flash memory]] chips using a "10{{nbsp}}nm-class" process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".<ref name="tomshardware">{{cite news |title=Samsung Mass Producing 128Gb 3-bit MLC NAND Flash |url=https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |access-date=21 June 2019 |work=[[Tom's Hardware]] |date=11 April 2013 |archive-date=21 June 2019 |archive-url=https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html |url-status=dead }}</ref> On 17 October 2016, [[Samsung Electronics]] announced mass production of [[System on a chip|SoC]] chips at "10&nbsp;nm".<ref>{{citation| url = https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology | title = Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology| date = Oct 2016 }}</ref> The technology's main announced challenge at that time had been [[multiple patterning|triple patterning]] for its metal layer.<ref>{{Cite web|url=https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology|title=Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology|website=news.samsung.com}}</ref><ref>{{Cite web|url=http://www.cse.cuhk.edu.hk/~byu/papers/N01-SPIE-TPL.pdf|title=triple patterning for 10nm metal}}</ref>{{and then what|date=February 2024}}

[[TSMC]] began commercial production of "10&nbsp;nm" chips in early 2016, before moving onto mass production in early 2017.<ref name="tsmc">{{cite web |title=10nm Technology |url=https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm |publisher=[[TSMC]] |access-date=30 June 2019}}</ref>

On 21 April 2017, Samsung started shipping their [[Galaxy S8]] smartphone, which used the company's version of the "10&nbsp;nm" processor.<ref>{{Cite web | url=http://www.samsung.com/us/explore/galaxy-s8/buy/ | title=Buy}}</ref>{{and then what|date=February 2024}} On 12 June 2017, Apple delivered second-generation [[iPad Pro]] tablets powered with TSMC-produced [[Apple A10X]] chips using the "10&nbsp;nm" FinFET process.<ref>{{Cite web|url=http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/|title=10nm Rollout Marching Right Along|last=techinsights.com|website=techinsights.com|access-date=2017-06-30|archive-url=https://web.archive.org/web/20170803141307/http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/|archive-date=2017-08-03|url-status=dead}}</ref>

On 12 September 2017, Apple announced the [[Apple A11]], a 64-bit ARM-based system on a chip, manufactured by TSMC using a "10&nbsp;nm" FinFET process, containing 4.3 billion transistors on a die of 87.66&nbsp;mm<sup>2</sup>.

In April 2018, Intel announced a delay in volume production of "10&nbsp;nm" mainstream CPUs until sometime in 2019.<ref>{{cite web|url=https://www.fool.com/investing/2018/04/29/intel-corp-delays-10nm-chip-production.aspx|title=Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019.|date=2018-04-29|access-date=2018-08-01}}</ref> In July, the exact time was further pinned down to the holiday season.<ref>{{cite news|url=https://arstechnica.com/gadgets/2018/07/intel-says-not-to-expect-mainstream-10nm-chips-until-2h19/|title=Intel says not to expect mainstream 10nm chips until 2H19|date=2018-07-28|access-date=2018-08-01}}</ref> In the meantime, however, they did release a low-power "10&nbsp;nm" mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.<ref>{{cite web|url=https://www.tomshardware.com/news/intel-10nm-processor-core-i3-8121u,37054.html|title=Intel's First 10nm Processor Lands In China|date=2018-05-15|access-date=2018-09-11}}</ref>{{and then what|date=February 2024}}

In June 2018 at VLSI 2018, Samsung announced their "11LPP" and "8LPP" processes. "11LPP" was a hybrid based on Samsung "14&nbsp;nm" and "10&nbsp;nm" technology. "11LPP" was based on their "10&nbsp;nm" BEOL, not their "20&nbsp;nm" BEOL like the "14LPP". "8LPP" was based on the "10LPP" process.<ref>{{Cite web|url=https://fuse.wikichip.org/news/1425/vlsi-2018-samsungs-11nm-11lpp/|title=VLSI 2018: Samsung's 11nm nodelet, 11LPP|date=2018-06-30|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}</ref><ref name=":0">{{Cite web|url=https://fuse.wikichip.org/news/1443/vlsi-2018-samsungs-8nm-8lpp-a-10nm-extension/|title=VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension|date=2018-07-01|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}</ref>{{and then what|date=February 2024}}

Nvidia released their [[GeForce 30 series]] GPUs in September 2020. They were at that time made on a custom version of Samsung's "8&nbsp;nm" process, called "Samsung 8N", with a transistor density of 44.56 million transistors per mm<sup>2</sup>.<ref>{{Cite news|url=https://www.pcgamer.com/amp/nvidia-ampere-samsung-8nm-process/|title=Nvidia confirms Samsung 8nm process for RTX 3090, RTX 3080, and RTX 3070 {{pipe}} PC Gamer|website=www.pcgamer.com|date=September 2020 |last1=James |first1=Dave }}</ref><ref>{{Cite web|url=https://wccftech.com/nvidia-geforce-rtx-30-series-ampere-graphics-cards-deep-dive/|title=NVIDIA GeForce RTX 30 Ampere GPU Deep-Dive, Full Specs, Thermals, Power & Performance Detailed|date=September 4, 2020}}</ref>{{and then what|date=February 2024}}

==Process nodes==
===Foundry===
{| class="wikitable" style="text-align:center;"
!
! colspan="2" | ITRS Logic Device<br />Ground Rules (2015)
! colspan="5" | [[Samsung Electronics|Samsung]]
! [[TSMC]]
! colspan="2" | [[Intel]]
|-
! style="text-align:left;" | Process name
| 16/14&nbsp;nm
| 11/10&nbsp;nm
| 10LPE<br />(10&nbsp;nm) || 10LPP<br />(10&nbsp;nm) || 8LPP<br />(8&nbsp;nm) || 8LPU<br />(8&nbsp;nm) || 8LPA<br />(8&nbsp;nm)
| 10FF<br />(10&nbsp;nm)
| 10nm<ref>{{cite web|url=https://www.semiaccurate.com/2018/08/02/intel-guts-10nm-to-get-it-out-the-door/|title=Intel guts 10nm to get it out the door|last=Demerjian|first=Charlie|date=2018-08-02|work=SemiAccurate|access-date=6 September 2024}}</ref> || 10nm SF<br />(10&nbsp;nm){{efn|For 10nm ESF renamed ''Intel 7'', see [[7 nm process|7 nm]]<ref>{{cite web | url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros | title=Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! }}</ref>{{disputed inline|Intel 7|date=September 2023}}}}
|-
!Transistor density (MTr / mm<sup>2</sup>)
|{{Unknown}}
|{{Unknown}}
|colspan="2" | 51.82<ref name=":0" /> ||colspan="2" | 61.18<ref name=":0" /> || {{Unknown}}
|52.51<ref>{{Cite web|url=https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/|title=TSMC Announces 6-Nanometer Process|last=Schor|first=David|date=2019-04-16|website=WikiChip Fuse|language=en-US|access-date=2019-05-31}}</ref>
|colspan="2" |100.76<ref>{{Cite news|url=https://hexus.net/tech/news/cpu/119699-intel-10nm-density-27x-improved-14nm-node/|title=Intel 10nm density is 2.7X improved over its 14nm node|work=HEXUS|access-date=2018-11-14|language=en-GB}}</ref>{{efn|Intel uses this formula:<ref>{{Cite web|url=https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/|title=Let's Clear Up the Node Naming Mess|last=Bohr|first=Mark|date=2017-03-28|website=Intel Newsroom|access-date=2018-12-06}}</ref> <math>\rm No.\ Transistors / mm^2 = 0.6 \cdot \frac{\rm NAND2\ Tr\ Count}{\rm NAND2\ Cell\ Area} + 0.4 \cdot \frac{\rm Scan\ Flip\ Flop\ Tr\ Count}{\rm Scan\ Flip\ Flop\ Cell\ Area}</math>}}
|-
! style="text-align:left;" | Transistor gate pitch (nm)
| 70
| 48
| colspan="2" | 68 || colspan="2" | 64 || {{Unknown}}
| 66
| colspan="2" | 54
|-
! style="text-align:left;" | Interconnect pitch (nm)
| 56
| 36
| colspan="2" | 51 || colspan="2" {{Unknown}} || {{Unknown}}
| 44
| colspan="2" | 36
|-
! style="text-align:left;" | Transistor fin pitch (nm)
| 42
| 36
| colspan="4" | 42 || {{Unknown}}
| 36
| colspan="2" | 34
|-
! style="text-align:left;" | Transistor fin height (nm)
| 42
| 42
| colspan="2" | 49 || colspan="2" {{Unknown}} || {{Unknown}}
| 42
| colspan="2" | 53
|-
! style="text-align:left;" | Production year
| 2015
| 2017
| {{yes|2016 Q4 production}}<ref>{{Cite web|url=https://www.anandtech.com/show/10765/samsung-10nm-massproduction|title=Samsung Foundry Announces 10nm SoC In Mass-Production|first=Andrei|last=Frumusanu|website=www.anandtech.com}}</ref> || {{yes|2017 Q4 production}}<ref>{{Cite web|url=https://www.anandtech.com/show/12096/samsung-starts-10lpp-mass-production|title=Samsung Starts Mass Production of Chips Using 10nm Low Power Plus (10LPP) Process Tech|first=Anton|last=Shilov|website=www.anandtech.com}}</ref> || {{yes|2018 production}} || {{yes|2018 risk production}}<br />2019 production<ref>{{Cite web|url=https://www.anandtech.com/show/13329/samsung-foundry-updates-8lpu-for-2019|title=Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019|first=Anton|last=Shilov|website=www.anandtech.com}}</ref> || {{yes|2021 production}}
| {{yes|2016 risk production}}<ref name="tsmc" /><br />2017 production<ref name="tsmc" />
| {{yes|2018 production}} <br />([[Cannon Lake (microarchitecture)|Cannon Lake]])<ref name=":3">{{Cite web |last=Cutress |first=Ian |date=July 26, 2021 |title=Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?! |url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros |website=AnandTech |access-date=2021-07-27}}</ref>
| {{yes|2020 production}} <br />([[Tiger Lake]])<ref>{{cite web | url=https://www.anandtech.com/show/16107/what-products-use-intel-10nm-superfin-demystified/3 | title=What Products Use Intel 10nm? SuperFin and 10++ Demystified }}</ref>
|}
{{notelist}}
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their "10&nbsp;nm" process as having a 64&nbsp;nm transistor gate pitch and 48&nbsp;nm interconnect pitch. TSMC reported their "10&nbsp;nm" process as having a 64&nbsp;nm transistor gate pitch and 42&nbsp;nm interconnect pitch. Further investigation by Tech Insights revealed even these values to also be false, and they have been updated accordingly. In addition, the transistor fin height of Samsung's "10&nbsp;nm" process was updated by MSSCORPS CO at SEMICON Taiwan 2017.<ref>{{Cite web|url=http://hothardware.com/news/intel-details-advanced-10nm-node|title=Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals|date=2017-03-28|access-date=2017-03-30|archive-date=2017-03-30|archive-url=https://web.archive.org/web/20170330151945/http://hothardware.com/news/intel-details-advanced-10nm-node|url-status=dead}}</ref><ref>{{Cite web|url=https://www.semiconductors.org/wp-content/uploads/2018/06/0_2015-ITRS-2.0-Executive-Report-1.pdf|title=International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report|access-date=2018-12-27}}</ref><ref>{{Cite web|url=https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now/|title=14nm 16nm 10nm and 7nm - What we know now|first=Scotten|last=Jones|date=25 February 2024 }}</ref><ref name=TI-Sam-10LPE>{{Cite web|url=http://www.techinsights.com/about-techinsights/overview/blog/qualcomm-snapdragon-835-first-to-10-nm/|title=Qualcomm Snapdragon 835 First to 10&nbsp;nm |quote=Samsung 10LPE process }}</ref><ref name=wikichip-10>{{Cite web|url=https://en.wikichip.org/wiki/10_nm_lithography_process|title=10 nm lithography process |website=wikichip}}</ref> GlobalFoundries decided not to develop a "10&nbsp;nm" node, because it believed it would be short lived.<ref>{{Cite web|url=https://semiwiki.com/semiconductor-manufacturers/globalfoundries/6879-exclusive-globalfoundries-discloses-7nm-process-detail/|title=Exclusive - GLOBALFOUNDRIES discloses 7nm process detail|first=Scotten|last=Jones|date=25 February 2024 }}</ref> Samsung's "8&nbsp;nm" process was at that time the company's last to exclusively use DUV lithography.<ref>{{Cite web|url=https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production|title=Samsung's 8LPP Process Technology Qualified, Ready for Production|first=Anton|last=Shilov|website=www.anandtech.com}}</ref>{{and then what|date=February 2024}}

==DRAM "10 nm class"==
{{main|Dynamic random-access memory}}
For the DRAM industry, the term "10&nbsp;nm-class" is often used and this dimension generally refers to the half-pitch of the active area.{{citation needed|date=April 2019}} The "10&nbsp;nm" foundry structures are generally much larger.{{citation needed|date=April 2019}}

Generally "10&nbsp;nm class" refers to DRAM with a 10-19&nbsp;nm feature size, and was first introduced {{Circa|2016}}. As of 2020, there were three generations of "10&nbsp;nm class" DRAM : 1x&nbsp;nm (19-17&nbsp;nm, Gen1); 1y&nbsp;nm (16-14&nbsp;nm, Gen2); and 1z&nbsp;nm (13-11&nbsp;nm, Gen3).<ref>{{citation| url  =https://blocksandfiles.com/2020/04/13/dram-is-stuck-in-a-10nm-process-trap/ | title = Why DRAM is stuck in a 10nm trap | first = Chris | last = Mellor |date = 13 April 2020 | work = blocksandfiles.com }}</ref> 3rd Generation "1z" DRAM was first introduced {{Circa|2019}} by [[Samsung]], and was initially stated to be produced using ArF lithography without the use of EUV lithography;<ref>{{citation| url  = https://www.anandtech.com/show/14118/samsung-develops-8-gb-drams-using-3rd-gen-10nmclass-process-technology | title  =Samsung Develops Smaller DDR4 Dies Using 3rd Gen 10nm-Class Process Tech | first =  Anton | last = Shilov | date  =21 March 2019 | work = www.anandtech.com }}</ref><ref>{{citation | url  =https://news.samsung.com/my/samsung-develops-industrys-first-3rd-generation-10nm-class-dram-for-premium-memory-applications | title  =Samsung Develops Industry's First 3rd-generation 10nm-Class DRAM for Premium Memory Applications | date = 25 Mar 2019 | publisher = Samsung | type = press release }}</ref> subsequent production did utilise EUV lithography.<ref>{{citation | url  = https://news.samsung.com/my/samsung-announces-industrys-first-euv-dram-with-shipment-of-first-million-modules| title  =Samsung Announces Industry's First EUV DRAM with Shipment of First Million Modules| date = 25 Mar 2020 | publisher = Samsung | type = press release }}</ref>

Beyond 1z Samsung named its next node (fourth generation "10&nbsp;nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022){{and then what|date=February 2024}}; whilst [[Micron Technology|Micron]] referred{{and then what|date=February 2024}} to succeeding "nodes" as "D1α" and "D1β".<ref>{{citation|url =https://www.eetimes.com/teardown-samsungs-d1z-dram-with-euv-lithography/| work = www.eetimes.com | first  = Jeongdong | last = Choe |date= 18 Feb 2021 |title = Teardown: Samsung's D1z DRAM with EUV Lithography}}</ref> Micron announced volume shipment of 1α class DRAM in early 2021.<ref>{{citation|url  =https://investors.micron.com/news-releases/news-release-details/micron-delivers-industrys-first-1a-dram-technology | title = Micron Delivers Industry's First 1α DRAM Technology | date = 26 Jan 2021 | publisher = Micron| type =press release }}</ref>

==References==
{{reflist|30em}}

{{sequence
| prev=[[14 nm process|14 nm]]
| next=[[7 nm process|7 nm]]
| list=[[MOSFET]] [[Semiconductor device fabrication|manufacturing processes]]
}}
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{{DEFAULTSORT:10 nanometre}}
[[Category:International Technology Roadmap for Semiconductors lithography nodes|*00010]]